Radyne DMD2401 Operation Manual page 108

DMD2401/DMD2401L/DMD2401 IBS/IDR Satellite Modem
<4> Buffer Size
<1> Buffer Clock
Buffer Clock
<1> Polarity
<1> Operating Mode
<1> Alarm 1 Mask
<1> Alarm 2 Mask
<1> Alarm 3 Mask
<1> Alarm 4 Mask
<1> Common Alarm 1
Mask
<1> Reserved
TM065 - Rev. 3.3
Byte 1 - 2 = Buffer Size in ms
Byte 3 - 4 = Buffer Size in Bytes
0 = External, 1 = Internal, 2 = EXC, 3 = RX SAT
0 = Normal, 1 = Inverted
0 = Normal, 1 = 2047 Test
Bit 0 = Receive Processor Fault
Bit 1 = Signal Lock Fault
Bit 2 = Receive Satellite AIS Fault
Bit 3 = Rx AGC/Input Level Fault
Bit 4 = Reed-Solomon Sync Fault
Bit 5 = Reed-Solomon Excessive Errors Fault
Bit 6 = Reed-Solomon Uncorrectable Word Fault)
Bit 7 = Receive Forced Alarm
(0 = Mask, 1 = Allow)
Bit 0 = Buffer Underflow
Bit 1 = Buffer Overflow
Bit 2 = Buffer Under 10%
Bit 3 = Buffer Over 90%
Bit 4 = Receive FPGA Configuration Alarm Fault
Bit 5 = Rx LNB Fault, LBST Only
Bits 6 - 7 = Spares
(0 = Mask, 1 = Allow)
Bit 0 = IF Synthesizer Lock Detect Fault
Bit 1 = Rx Oversample PLL Lock Detect Fault
Bit 2 = Buffer Clock PLL Lock Detect Fault
Bit 3 = Viterbi Decoder Lock Fault
Bit 4 = Sequential Decoder Lock Fault
Bit 5 = Rx 2047 Test Pattern Lock Fault
Bit 6 = External Reference PLL Lock Fault
Bit 7 = Frame Sync/Multiframe Sync Loss
(0 = Mask, 1 = Allow)
Bit 0 = Buffer Clock Activity Detect Fault
Bit 1 = External BNC Activity Detect Fault
Bit 2 = Rx Satellite Clock Activity Detect Fault
Bit 3 = External Reference PLL Activity Fault
Bits 4 - 7 = Spares
(0 = Mask, 1 = Allow)
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Temperature
Bit 4 = Interface FPGA Fault
Bit 5 = Battery Fault
Bit 6 = RAM/ROM Fault
Bit 7 = Spare
(0 = Mask, 1 = Allow)
Set to Zero
User Interfaces
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