Radyne DMD2401 Operation Manual page 113

User Interfaces
<1> Latched Alarm 3
<1> Latched Alarm 4
<1> Latched Comm.
Alarm
<1> Reserved
<4> Error Counter
<4> Test 2047 Error
Counter
<2> Raw BER
Mantissa
<2> Corrected BER
Mantissa
<2> Eb/No
<4> Offset Frequency
<2> Test 2047
Mantissa
<1> Raw BER
Exponent
<1> Corrected BER
Exponent
<1> Test 2047 BER
4-74
DMD2401/DMD2401L/DMD2401 IBS/IDR Satellite Modem
Bit 4 = Receive FPGA Fault
Bit 5 = Rx LNB Fault, LBST Only
Bits 6 - 7 = Spares
(0 = Pass, 1 = Fail)
Bit 0 = IF Synthesizer Lock Detect Fault
Bit 1 = Rx Oversample PLL Lock Detect Fault
Bit 2 = Buffer Clock PLL Lock Detect Fault
Bit 3 = Viterbi Decoder Lock Fault
Bit 4 = Sequential Decoder Lock Fault
Bit 5 = Rx 2047 Test Pattern Lock Fault
Bit 6 = External Reference PLL Lock Fault
Bit 7 = Frame Sync Fault
(0 = Pass, 1 = Fail)
Bit 0 = Buffer Clock Activity Detect Fault
Bit 1 = External BNC Activity Detect Fault
Bit 2 = Rx Satellite Clock Activity Detect Fault
Bit 3 = External Reference PLL Activity Fault
Bits 4 - 7 = Spares
(0 = Pass, 1 = Fail)
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Temperature
Bit 4 = Interface FPGA Fault
Bit 5 = Battery Fault
Bit 6 = RAM/ROM Fault
Bit 7 = Spare
Ignore
Unsigned Binary Value
Unsigned Binary Value
Bytes 1 - 2 = Unsigned Binary Value Raw BER
Bytes 1 - 2 = Unsigned Binary Value Corrected BER
Unsigned Binary Value, 2 Decimal Places Implied
Unsigned Binary Value in Hz, Pos/Neg Indicated Below
Bytes 1 - 2 = Unsigned Binary Value Test 2047 BER
Byte 3 = Unsigned Binary Value Exponent
Byte 3 = Unsigned Binary Value Exponent
Byte 3 = Unsigned Binary Value Exponent
TM065 – Rev. 3.3