Nokia 9000i Service Manual page 62

RAE/RAK–1N
Baseband
Table 37. External Signals and Connections, Outputs
Signal Name
DSPCLKEN DSP clock circuit enable
RFICLK RFI master clock (13 MHz)
RFI2CLK RFI sleep clock (135.4 kHz)
CODEC_CLK PCM data clock (512 kHz)
PCMDATRCLKX Inverted PCM data clock (512 kHz)
used as input clock for Codec and DBUS interface
SYNC Bit sync clock (8 kHz)
PCMCOSYCLKX Bit sync clock (8 kHz), inverted
DCLK DBUS data clock (512 kHz)
DSYNC DBUS bit sync clock (8 kHz)
SIMCLK SIM data clock (3.25/1.625 MHz)
VSIM SIM power control
COL(3:0) Lines for keyboard column write
Table 38. External Signals and Connections, Bidirectional
Signal Name
DSPDA(15:0) DSP's 16–bit data bus
MCUDA(15:8) MCU's 8–bit data bus
RFIDA(11:0) RFI's 12–bit data bus
UIF(6:0) LCD–controller control and keyboard read bus
SIMDATA Serial data from/to SIM
Block description
PSL+ supplies the reset to the ASIC at power up. The ASIC starts the
clocks to the DSP and the MCU. MCU and RFI reset is released after 256
13 MHz clock cycles. DSP reset release time from DSP clock activation
can be selected from 0 to 255 13MHz clock cycles. In our case 255 is
selected. SIM reset release time is according to GSM SIM specifications.
The RFC buffer buffers the 26 MHz clock from theVCXO to the ASIC. In
the ASIC the clock is further buffered and delivered to MCU. The clock is
also divided and delivered to RFI and SIM. ASIC also generates main and
sync clocks for audio codec, DSP's SIOs and DBUS. The clock outputs
can be disabled in order to save current when the clock is not needed.
Also the 60.2 MHz DSP oscillator can be disabled by the ASIC.
Page 2–36
Signal description
Signal description
After Sales
Technical Documentation
(continued)
To
DSPU
RFI
RFI
DSPU, AU-
DIO
DSPU
AUDIO
DSPU
DSPU
DSPU
SIMFLEX
Conn.
SIMFLEX
Conn.
B2B Conn.
To/From
DSPU
CTRLU
RFI
B2B Conn.
SIMFLEX
Conn.
Original, 08/96