Memory Map - Nokia 9000i Service Manual

After Sales
Technical Documentation
DRAM area is composed of a single 1M x 16 bit chip. The access time of
70 ns enables zero wait–state page access and one wait–state page fault.
FLASH memory is used for two purposes on this device. Two 1M x 16 bit
chips (75 ns) are used for BIOS, DOS, GEOS and applications this
memory is usually called XIP FLASH. A 1M x 16 bit chip (120 ns) is used
to save user data. This memory device is handled by FLASH file system.
From application point of view this memory is accessed like hard disk
using INT13 functions. 75 ns FLASH device needs one wait–state and
120 ns device two wait–states.
FLASH devices are equipped with Reset/Power down pin (RP#) which can
be used to place devices in a Deep PowerDown state. RP# pin of two XIP
FLASH devices is connected to SUSPEND pin of E3G. SUSPEND# pin is
active when E3G is in SUSPEND mode and internal PLL's are not runnig.
RP# pin of the FLASH device under TFFS is connected to a GPIO pin and
it is controlled by TFFS. TFFS and RS232 flash download softwares are
able to control 5V power supply powerdown. There is 100us delay needed
between 5V power up and write command.
1 Mbyte of address space is directly addressable by the CPU
(conventional memory). Any additional memory is accessed via Expanded
Memory System EMS . EMS system follows LIM 4.0 specification.

Memory Map

Table 18.
000000 Interrupt Vector, DOS data (DRAM)
00FFFF
010000 GEOS heap (DRAM)
07FFFF
09E400 True FFS data (DRAM)
0A03FF
0A0400 BIOS data (DRAM)
0A05FF
0A0600 Video buffer (DRAM)
0AFFFF
0B0000 EMS page 0 (True FFS & GEOS ROM
disk)
0B3FFF
0B4000 EMS page 1 (XIP page 2)
0B7FFF EMS register
Original, 08/96
Memory Map
RAE/RAK–1N
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