Functional Description; Introduction; Clocking Scheme; Reset And Power Management - Nokia 9000i Service Manual

RAE/RAK–1N
PDA Hardware

Functional Description

Introduction

Intel E3G is 386 based core with all needed peripherals on same chip.
E3G is used to execute all applications, GEOS, DOS, BIOS, and TFFS.

Clocking Scheme

Actual clock signals are not routed to any other chip than previously
mentioned E3G. All clocks are generated from a 32.768 kHz chrystal with
PLL's integrated to the E3G CPU chip.
System clock rates are as follows:
CPU core
UART's
8254 Timer
RTC

Reset and Power Management

Power good (PWRGOOD) signal from PDAPWRU module is used as a
system reset. Both PDA and CMT modules power management system is
implemented with special hardware in close co–operation with operating
system.
POWER SUPPLY
5 V Power supply
5VPDX
LCD Power supply
LCDVCCON
LCDPVEEON
3.3 V Power supply
PWRGOOD
GND
LIDOPEN (CMT)
Figure 2.
Page 6 – 18
23.96 MHz
1.84MHz
1.198MHz
32.768kHz
Integrated CPU
I/O
LCDVCCON
LCDPVEEON
RESET
PMI PMI
Note 1.
LID SWITCH
VL1
Reset and power management block diagram
Technical Documentation
E3G
CPU
I/O
I/O
SUS–
PEND I/O
PowerDown PowerDown
1M x 16 1M x 16
FLASH
FLASH
"XIP" FLASH FLASH file system
Original, 08/96
After Sales
IR tranceiver
Shutdown
RS232 Buffer
Shutdown
Enable