Interrupts; Table 4-23 Interrupt I/O Descriptions - Silicon Graphics 1400 Server Family Maintenance And Upgrade Manual

Interrupts

Table 4-23 recommends the logical interrupt mapping of interrupt sources; it reflects a
typical configuration, but these interrupts can be changed by the user. Use the
information to determine how to program each interrupt. The actual interrupt map is
defined using configuration registers in the PIIX4E and the I/O controller. I/O
Redirection Registers in the I/O APIC are provided for each interrupt signal; the signals
define hardware interrupt signal characteristics for APIC messages sent to local APIC(s).
Note: To disable either IDE controller and reuse the interrupt: if you plan to disable
either IDE controller to reuse the interrupt for that controller, you must physically
unplug the IDE cable from the board connector (IDE0) if a cable is present. Simply
disabling the drive by configuring the SSU option does not make the interrupt available.
Table 4-23 Interrupt I/O Descriptions
Interrupt I/O APIC level
INTR INT0
NMI N/A
IRQ1 INT1
Cascade INT2
IRQ3 INT3
IRQ4 INT4
IRQ5 INT5
IRQ6 INT6
IRQ7 INT7
IRQ8_L INT8
IRQ9 INT9
IRQ10 INT10
IRQ11 INT11
Description
Processor interrupt
NMI from PIC to processor
Keyboard interrupt
Interrupt signal from second 8259 in PIIX4E
Serial port A or B interrupt from SIO device (user can
configure)
Serial port A or B interrupt from SIO device (user can
configure)
Parallel port II
Diskette port
Parallel port
RTC interrupt
Signal control interrupt (SCI) used by ACPI-compliant
OS
Interrupts
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