Pci Express* Initialization; Pci Express* Enhanced Configuration Mechannisms; Legacy Universal Serial Bus (Usb) Initialization; Ide Initialization - Intel SE7520AF2 Technical Product Specification

System BIOS
5.5.9

PCI Express* Initialization

The following describes the PCI Express* initialization performed by the BIOS.
5.5.10

PCI Express* Enhanced Configuration Mechannisms

The PCI Express* extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI 2.3 configuration space. PCI Express* configuration
space is divided into a PCI 2.3 compatible region and an extended PCI-E region.
The Enhanced Configuration memory address map is positioned into memory space by use of
the PCI Express* Enhanced Configuration Base register, known as EXPECBASE, which
corresponds to E000 0000h. Users must access this space in double byte units.
0XFFFFFF
Bus 255
0X1FFFF
Bus1
0XFFFF
Bus 0
0
Located by PCI-E base address
Figure 33. Enhanced Configuration Memory Address Map
5.5.11

Legacy Universal Serial Bus (USB) Initialization

The BIOS supports PS/2* emulation of USB 1.1 keyboards and mice. During POST, the BIOS
initializes and configures the root hub ports and then searches for a keyboard and mouse. The
USB hub enables them.
5.5.12

IDE Initialization

The BIOS supports the ATA/ATAPI Specification, version 6 or later. The BIOS initializes the
embedded IDE controller in the ICH5-R and the IDE devices that are connected to these
devices. The BIOS scans the IDE devices and programs the controller and the devices with
their optimum timings. The IDE disk read/write services that are provided by the BIOS use PIO
mode, but the BIOS programs the necessary Ultra DMA registers in the IDE controller so that
the operating system can use the Ultra DMA Modes.
116
Intel order number C77866-003
Intel® Server Board SE7520AF2 TPS
0XFFFF
0X7FFF
0X1FFF
0XFFF
Device1 Function 0
Device0 Function2
Device0 Function1
Device0 Function0
Revision 1.2