Table 92. Bootblock Recovery Code Checkpoints - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
Diagnostic LED
Decoder
Check
G=Green, R=Red,
point
A=Amber
Hi
D2
R R G
D3
R R G
D4 R A Off
D5
R A Off
D6
R A G
D7
R A G
D8
A R Off
D9
A R Off
DA
A R G
E1-E8
- - -
EC-EE
7.3.1.5 Bootblock Recovery Code Checkpoints
The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery
needs to occur because the user has forced the update or the BIOS checksum is corrupt. The
following table describes the type of checkpoints that may occur during the Bootblock recovery
portion of the BIOS:
Diagnostic LED
Decoder
Check
G=Green, R=Red,
point
A=Amber
Hi
E0
R R R
E9 A R R
EA A R A
Revision 1.2
Low
Disable CACHE before memory detection. Execute full memory sizing module.
R
Verify that flat mode is enabled.
If memory sizing module not executed, start memory refresh and do memory
A sizing in Bootblock code. Do additional chipset initialization. Re-enable CACHE.
Verify that flat mode is enabled.
R Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
Bootblock code is copied from ROM to lower system memory and control is
A
given to it. BIOS now executes out of RAM.
Both key sequence and OEM specific method is checked to determine if BIOS
recovery is forced. Main BIOS checksum is tested. If BIOS recovery is
R
necessary, control flows to checkpoint E0. See Bootblock Recovery Code
Checkpoints section of document for more information.
Restore CPUID value back into register. The Bootblock-Runtime interface
A module is moved to system memory and control is given to it. Determine
whether to execute serial flash.
The Runtime module is uncompressed into memory. CPUID information is
R
stored in memory.
Store the Uncompressed pointer for future use in PMM. Copying Main BIOS
A into memory. Leaves all RAM below 1MB Read-Write including E000 and F000
shadow areas but closing SMRAM.
Restore CPUID value back into register. Give control to BIOS POST
R (ExecutePOSTKernel). See POST Code Checkpoints section of document for
more information.
OEM memory detection/configuration error. This range is reserved for chipset
- vendors and system manufacturers. The error associated with this value may be
different from one platform to the next.

Table 92. Bootblock Recovery Code Checkpoints

Low
Initialize the floppy controller in the super I/O. Some interrupt vectors are
Off initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1
cache is enabled.
G Set up floppy controller and data. Attempt to read from floppy.
Off Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
Intel order number C77866-003
Error Reporting and Handling
Description
Description
203