Single Bit Ecc Error Throttling Prevention - Intel SE7520AF2 Technical Product Specification

Error Reporting and Handling
Memory 33h
POST 31h
Error
System 03h
Event
System 03h
Event
Critical 31h
Interrupt
Critical 31h
Interrupt
7.2.4

Single Bit ECC Error Throttling Prevention

The system detects, corrects, and logs correctable errors. As long as these errors occur
infrequently, the system should continue to operate without a problem.
Occasionally, correctable errors are caused by a persistent failure of a single component. For
example, a broken data line on a DIMM would exhibit repeated errors until replaced. Although
these errors are correctable, continual calls to the error logger can throttle the system,
preventing any further useful work.
For this reason, the system counts certain types of correctable errors and disables reporting if
they occur too frequently. Correction remains enabled but calls to the error handler are
disabled. This allows the system to continue running, despite a persistent correctable failure.
The BIOS adds an entry to the event log to indicate that logging for that type of error has been
disabled. Such an entry indicates a serious hardware problem that must be repaired at the
earliest possible time.
The system BIOS implements this feature for two types of errors, correctable memory errors
and correctable bus errors. If ten errors occur in a single wall-clock hour, the corresponding
198
04h 0Ch 08h
04h 0Fh 06h
04h 12h 83h
04h 12h 83h
04h 13h EAh
04h 13h EBh
Intel order number C77866-003
Intel® Server Board SE7520AF2 TPS
6Fh 01h A1h
6Fh Data2[0: A0h or
3] Data2
6Fh 05h 05h
6Fh 01h 01h
6Fh 04h A4h
6Fh 05h A5h
Synrome
Data2: Uncorrectabl
DIMM e ECC
location
Data3:
Synrome
See POST POST Error
error code
table7.3.3.
Data2:low
byte
Data3:hig
h byte
Data2: Timestamp
Clock Sync
st
00h(1 of
pair)
nd
80h(2 of
pair)
Data3:0ffh
Data2:0ffh Boot event
log
Data3:0ffh
Data2:bus PCI SERR
num
Data3:dev
and fun
Data2:bus PCI PERR
num
Data3:dev
and fun
Revision 1.2