Clock Generation And Distribution; Table 29. Clock Generation And Distribution - Intel SE7520AF2 Technical Product Specification

Intel® Server Board SE7520AF2 TPS
determine which host bus agents they are, Agent 0 or Agent 6, according whether their
BREQ0_L or BREQ1_L is asserted. This determines bus arbitration priority and order.
The processor(s) in the system determines which processor will be the BSP by using Bootstrap
Inter Processor Interrupts (BIPI) on the APIC data bus. The non-BSP processor becomes an
application processor and idles, waiting for a Startup Inter Processor Interrupt (SIPI). The BSP
begins by fetching the first instruction from the reset vector FFFFFFF0h. The Intel® E7520
chipset registers are updated to reflect memory configuration, all SDRAM is sized and
initialized. All PCI and ISA I/O subsystems are initialized and prepared for booting.
3.6

Clock Generation and Distribution

The main clock source is the CK409B synthesizer/driver component. This device generates
majority of the clocks in the design, including the serial reference clock source provided to the
DB800 differential buffer. Individual serial reference clocks required for PCI Express*
devices/slots are then generated by the DB800. All buses on the Intel® Server Board
SE7520AF2 operate using synchronous clocks. Clock synthesizer/driver circuitry on the
baseboard generates clock frequencies and voltage levels as detailed in the following table.
CK409B Clk
14MHz
33MHz
48MHz
66MHz
100 MHz
166MHz
DB800 Clk
100MHz
Revision 1.2

Table 29. Clock Generation and Distribution

Pin
REF1
REF0
PCIF0
PCIF1
PCIF2
PCI0
USB_48
DOT_48
3V66_0
3V66_1
SRC_P
SRC_N
CPU0
CPU0_N
CPU1
CPU1_N
CPU2
CPU2_N
CPU3
CPU3_N
Pin
DIF_0_P
DIF_0_N
DIF_1_P
DIF_1_N
Intel order number C77866-003
Device
ICH5R
Video
ICH5R
SIO3
IMM
Video – ATI Rage XL
ICH5R
SIO3
MCH
ICH5R
DB800
DB800
MCH
MCH
CPU2
CPU2
CPU1
CPU1
XDP
XDP
Device
ICH5R
ICH5R
MCH
MCH
Functional Architecture
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