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Intel® 5000 Series Chipsets Server Board Family Datasheet
4.17.6
System Memory Monitoring and System Boot
The following sequence of events describes the system booting process with respect to the
system memory monitoring feature.
During system boot, BIOS will determine the DIMM population and set this state in the
BMC. The BMC initializes the DIMM sensor state based on the discovered presence
information and persistent fault information.
BIOS will configure memory, disabling DIMMs as necessary and configure the RAS
features as required. The BIOS communicates the set of disabled DIMMs to the BMC
and the BIOS then communicates the RAS feature configuration (enabled / disabled
features) to the BMC.
The BIOS will then notify BMC to any one of the three redundancy states as defined in
section 4.17.5.1.
The BIOS will test the memory. For any memory errors that cause the BIOS to disable a
DIMM or generate an error event, the BIOS will notify the BMC of DIMM failure.
The BIOS must enable BMC system memory error monitoring.
4.18 PCI Express* Support
4.18.1
PCI Express Link Sensors
The BMC implements a series of sensors of IPMI type Critical Interrupt that are used to log run-
time PCI Express link errors detected by the BIOS. An entity ID in the SDR records associates
the errors with PCI Express per the IPMI entity ID definitions.
When the BIOS detects an error, it communicates this to the BMC.
If an error state is asserted on one of the PCI Express* sensors, the BMC will set the Front
panel fault LED to indicate a degraded condition. The sensor state is deasserted for the
following reasons:
The sensor is rearmed through an IPMI command.
The system is reset or powered-on.
Deassertion of the sensor state will remove that state as a contribution to the front panel fault
LED.
4.18.2
BMC Self-test
The BMC performs various tests as part of its initialization. If a failure is determined (e.g.,
corrupt BMC SDR), the BMC stores the error internally. BMC or BMC sub-system failures
detected during regular BMC operation may also be stored internally.
Revision 1.1
Intel order number D38960-004
System Management
127
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