Spi Debug Control Register And Msata/Pcie Select Control Register; Adm - Adc Control/Status Register; This Register Is Used As The Interrupt Control/Status Register For The Ti Ads8668A And Is Primarily Related To The Alarm Signal Output From The A/D - VersaLogic VL-EPU-4562 Reference Manual

SPI D C R
EBUG ONTROL
This register is only used to set an SPI loopback (debug/test only) but is also used for the
mSATA/PCIe Minicard Mux select.
Table 15: SPI – SPI Debug Control Register
Bit Identifier Access
RO
7 Reserved
R/W
6-4 MUXSEL(2:0)
RO
3 Reserved
R/W
2 SERIRQEN
R/W
1 SPILB
RO
0 Reserved
ADM – ADC C
ONTROL
This register is used as the interrupt control/status register for the TI ADS8668A and is
primarily related to the ALARM signal output from the A/
Bit Identifier Access
7 IRQEN
EPU-4562 Programmer's Reference Manual
SATA/PCI
EGISTER AND M
Default
0 Reserved. Writes are ignored; reads always return 0.
mSATA/PCIe Mux selection for Minicard slot (and 2
connector):
•
000 – Select mSATA using only pin 43 (MSATA_DETECT). This
is an Intel-mode that is reliable for PCIe Minicards but not for
mSATA modules that inadvertently ground this signal.
•
001 – Use only Pin 51 (PRES_DISABLE2#). This is the default
method and is defined in the Draft mSATA spec but some
Minicards use it as a second wireless disable.
•
010 – Use either Pin 43 or Pin 51. This will work just like 001
000
because Pin 43 is disabled by an FPGA pull-down.
•
011 – Force PCIe mode on the Minicard
•
100 – Force mSATA mode on the Minicard.
•
101 – Undefined (same as 000)
•
110 – Undefined (same as 000)
•
111 – Undefined (same as 000)
Note: When the Minicard uses PCIe, the SATA channel automatically
switches to the SATA connector.
0 Reserved. Writes are ignored; reads always return 0.
When an IRQ is assigned a slot in the SERIRQ, it will drive the slot
with the interrupt state, but this bit must be set to a '1' to do that.
0 – Slots assigned to SERIRQ are not driven (available for other
devices).
0
1 – Slots assigned to SERIRQ are driven with their current interrupt
state (which is low since interrupts are high-true).
This is because the default interrupt settings in this FPGA can conflict
with other interrupts if the VersaAPI is not being used (for example,
console redirect using IRQ3).
Debug/Test Only: Used to loop SPI output data back to the input
(debug/test mode).
0 – Normal operation
0
1 – Loop SPI output data back to the SPI input data (data output still
active)
0 Reserved. Writes are ignored; reads always return 0.
/S R
TATUS EGISTER
Default
R/W ADC ALARM Interrupt Enable/Disable.
0 – Interrupts disabled
0
1 – Interrupts enabled.
Note: This is essentially the interrupt mask.
S C R
E ELECT ONTROL EGISTER
Description
D.
Description
FPGA Registers
nd
SATA
21