Revision Indicator Register; Watchdog Timer Hold-Off Register - VersaLogic VSBC-8 Reference Manual

Revision Indicator Register

REVIND (READ ONLY) 00E1h (or 1E1h via CMOS Setup)
D7
PC4
This register is used to indicate the revision level of the VSBC-8 product.
Bit Mnemonic
D7-D3 PC4-PC0
D2 TC0
D1-D0 REV1-REV0

Watchdog Timer Hold-Off Register

WDHOLD (WRITE ONLY) 00E1h (or 1E1h via CMOS Setup)
D7
0
A watchdog timer circuit is included on the
if proper software execution fails or a hardware malfunction occurs. The watchdog timer is
controlled by the SCR.
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (1000 ms minimum). Writing a 5Ah to WDHOLD resets the
watchdog timeout period.
VSBC-8 Reference Manual
D6 D5 D4
PC3 PC2 PC1
Description
Product Code — These bits are hard coded to represent the product type. The
VSBC-8 will always read as 00001. Other codes are reserved for future products.
PC4 PC3 PC2
0 0 0
Note! These bits are read-only.
Throttling Code — This bit specifies how throttling is enabled at power-up and
reset.
0 = VSBC-8c
VSBC-8d
1 = VSBC-8b
VSBC-8e
Note! This bit is read-only.
Revision Level — These bits are represent the VSBC-8 circuit revision level.
REV1 REV0 Revision Level
0 0
0 1
1 0
1 1
Note! These bits are read-only.
D6 D5 D4
1 0
D3 D2
PC0 TC0
PC1 PC0 Product Code
0 1 VSBC-8
No Throttling
Throttling set at 37.5%
Initial product release
Reserved
Reserved
Reserved
D3 D2
1 1 0
board to reset the CPU and/or generate a NMI
VSBC-8
Revision Indicator Register
D1 D0
REV1 REV0
D1 D0
1 0
Reference – 49