Downstream I/O Address And Upstream I/O Address Registers - Intel 21555 User Manual

List of Registers
Table 49. Configuration CSR (Sheet 2 of 2)
This register is also mapped in memory and I/O space.
• Primary byte offset: 93:92h
• Secondary byte offset: 93:92h
• CSR byte offset: 013:012h
Bit Name
Upstream
9 Configuration
Control
Upstream
10 Self
Enable
15:11 Reserved
Table 50. Downstream I/O Address and Upstream I/O Address Registers
The Downstream I/O Address register is used for I/O transactions to be initiated on the secondary bus, and
the Upstream I/O Address register is used for I/O transactions to be initiated on the primary bus. The
downstream register can be written from the primary interface only and the upstream register can be written
from the secondary interface only
Offset
Byte
Bit
31:0
144
R/W Description
Enables the 21555 to perform upstream indirect configuration
transactions.
• When 0, the 21555 will not initiate a configuration transaction on the
R/W
• When 1, the 21555 is enabled to perform upstream configuration
• Reset value is 0
Controls the 21555 ability to respond to a configuration transaction that it
generates as a master.
• When 0, the 21555 does not respond to configuration transactions
-
Response R/W
• When 1, the 21555 does not respond to configuration transactions
• Reset value is 0
R Reserved. Reads only as 0.
.
Downstream I/O Address
017:014h
Name R/W
DIA:
R/(WP)
IO_ADDR (IA)
UIA:
R/(WS)
primary interface when the Upstream Configuration Data register is
accessed. The Upstream Configuration Data register is treated as a
reserved register.
transactions when the Upstream Configuration Data register is
accessed.
that it generates. These transaction end in master abort.
that it generates as a master.
Upstream I/O Address
1F:1Ch
Description
This register contains the address for an I/O transaction to be
generated on the target bus. The address is driven exactly as written
in this register. This register should be written before the Downstream
or Upstream I/O Data register is accessed. Once the Downstream or
Upstream I/O Data register is written or read, the transaction is
initiated on the secondary bus. When the semaphore method is used,
a master should not write to this register unless the master has
successfully read a 0 from the Downstream or Upstream I/O Own bit.
Reset value is 0
21555 Non-Transparent PCI-to-PCI Bridge User Manual