Downstream And Upstream Configuration Address Registers - Intel 21555 User Manual

Table 46. Downstream and Upstream Configuration Address Registers
This section describes both the downstream and upstream versions of the registers. These
registers are also mapped in memory and I/O space.
Offsets
Primary byte
Secondary byte
CSR Space
Bit Name
CFG_ADDR
31:0
(CA)
.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Downstream Configuration Address
83:80h
83:80h (Reserved)
003:000h
R/W Description
This register contains the address for a configuration transaction to be
generated on the target bus. The address is driven exactly as written in this
register. This register should be written before the corresponding
Downstream or Upstream Configuration Data register is accessed. Once
DCA:
the Downstream or Upstream Configuration Data register is accessed, the
R/(WP) transaction is initiated on the secondary or primary bus, respectively. When
the semaphore method is used, a master should not write to this register
unless the master has successfully read a 0 from the Downstream or
UCA:
Upstream Configuration Own bit.
R/(WS)
The Downstream Configuration Address register cannot be written from the
secondary interface.
The Upstream Configuration Address register cannot be written from the
primary interface.
List of Registers
Upstream Configuration Address
8B:88h (Reserved)
8B:88h
00B:008h
141