Intel 21555 User Manual page 158

List of Registers
Table 77. Chip Control 0 Register (Sheet 3 of 4)
This register may be preloaded by serial ROM or programmed by the local processor before host
configuration.
• Primary byte offset: CD:CCh
• Secondary byte offset: CD:CCh
Bit Name
Upstream
8 DAC Prefetch
Disable
Multiple
9
Device Enable
Primary
10 Access
Lockout
Secondary
11
Clock Disable
158
R/W Description
Controls prefetching for upstream dual address transactions using the
memory read bus command.
When 0, prefetching is performed for upstream DAC memory reads.
R/W
When 1, upstream DACs using the memory read bus command are not
prefetched; transactions are limited to a single Dword and byte enables
are preserved.
Reset value is 0
Enables multiple devices to be attached to the ROM interface.
• When 0, only the parallel and serial ROM can be attached to the ROM
interface. The PROM (PROM) chip select is driven on the pr_cs_l pin.
R/W
• When 1, multiple devices may be attached to the ROM interface. All
chip selects with the exception of the serial ROM are decoded from
the upper address lines of the ROM interface.
• Reset value is 0
This bit prevents the primary bus from accessing configuration space. This
allows the local processor to access the 21555 registers before the host
processor accesses them.
This bit can be written from the secondary interface only. The local
processor must write this bit to a 0 to allow the 21555 to be configured by
the host processor, unless preloaded to 0 by serial ROM.
R/(WS) • When 0, the 21555 configuration space can be accessed from both
interfaces.
• When 1, the 21555 configuration space can only be accessed from
the secondary interface. Primary bus accesses, with the exception of
Reset Control Register
the
• Reset value is 1 when pr_ad[3] is high during reset, 0 when pr_ad[3]
is low during reset.
Secondary clock output disable. (refer to
• When 0, signal s_clk_o is driven as a buffered copy of p_clk.
R/W
• When 1, signal s_clk_o is disabled and driven low.
• Reset value is 0 when pr_ad[5] is high during primary bus reset; 1
when pr_ad[5] is low during primary bus reset.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
, receive a target retry.
Table 20)