Intel 21555 User Manual page 123

Table 32. Configuration Space Address Register (Sheet 2 of 5)
Byte
Offset
(Hex)
2F:2E
6F:6E
33:30 (P)
73:70 (S)
34
74
37:35 (P)
77:75 (S)
3B:38 (P)
7B:78 (S)
3C (P)
7C (S)
3D (P)
7D (S)
3E (P)
7E (S)
3F (P)
7F (S)
45:44 (P)
05:04 (S)
47:46 (P)
07:06 (S)
4B:49 (P)
0B:09 (S)
4C (P)
0C (S)
4D (P)
0D (S)
53:50 (p)
13:10 (s)
57:54 (p)
17:14 (s)
5B:58 (P)
1B:18 (S)
5F:5C (P)
1F:1C (S)
63:60 (P)
23:20 (S)
67:64 (P)
27:24 (S)
73:70 (P)
33:30 (S)
7C(P)
3C (S)
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Register Name
Subsystem ID Register, page
154
Primary Expansion ROM BAR,
page 175
Enhanced Capabilities Pointer
Register, page 154
Reserved
Reserved
Primary and Secondary Interrupt
Line Registers, page 154
Primary and Secondary Interrupt
Pin Registers, page 155
Primary and Secondary Minimum
Grant Registers, page 155
Primary and Secondary
Maximum Latency Registers,
page 155
Primary and Secondary
Command Registers, page 149
Primary and Secondary Status
Registers, page 150
Primary and Secondary Class
Code Registers, page 152
Primary and Secondary Cache
Line Size Registers, page 152
Primary Latency and Secondary
Master Latency Timer Registers,
page 153
Secondary CSR Memory BAR
Secondary CSR I/O BAR
Upstream I/O or Memory 0 BAR
Upstream Memory 1 BAR
Upstream Memory 2 BAR
Reserved
Reserved
Primary and Secondary Interrupt
Line Registers, page 154
Reset Value
Preload
(Hex)
0000 Y
00000000 Via Setup
DC —
000000 —
00000000 —
00 —
01 —
00 Y
00 Y
0000
0290 —
068000 Y
00 —
00 —
00000000 —
00000001 —
00000000 Via Setup
00000000 Via Setup
Via Chip
00000000
Control 1
00000000 —
00000000 —
00 —
List of Registers
Write Read
Access Access
Secondary Y
Via Setup Y
N Y
N Y
N Y
Y Y
N Y
Secondary Y
Secondary Y
Y Y
N Y
Y Y
Y Y
Y Y
Y Y
Via Setup Y
Via Setup Y
Via Chip
Y
Control 1
N Y
N Y
Y Y
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