Intel 21555 User Manual page 108

Error Handling
Table 29. Parity Error Responses (Sheet 2 of 3)
Type of
Error
Data Parity
Error on
Primary
Bus
† PER: Parity Error Response bit (Primary | Secondary).
108
†
Type of PER
Action Taken
Transaction P|S
• Queues and forwards transaction with parity error.
0 | —
• Sets primary Parity Error Detected bit.
Downstream • Returns TRDY# (and STOP# when multiple data phases
Delayed requested).
Write
• Transaction not forwarded.
1 | —
• Sets primary Parity Error Detected bit.
• Asserts p_perr_l.
0 | — • Transaction completes normally on primary bus.
• Transaction completes normally on primary bus.
1 | —
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
Upstream
Delayed
• Transaction completes normally on primary bus.
Write
• Sets primary Data Parity Detected bit when p_perr_l is asserted.
1 | 1
• Asserts s_perr_l when returning s_trdy_l to initiator on secondary
bus (for both CSR and BAR forwarding mechanisms).
Downstream
— |
Delayed The 21555 is returning data, all action is taken by initiator.
—
Read
• Returns read data with bad parity to initiator (for both CSR and BAR
forwarding mechanisms).
0 | —
• Sets primary Parity Error Detected bit.
Upstream
• Returns read data with bad parity to initiator (for both CSR and BAR
Delayed
forwarding mechanisms).
Read
• Sets primary Parity Error Detected bit.
1 | —
• Sets primary Data Parity Detected bit.
• Asserts p_perr_l.
• Writes the data normally.
0 | —
• Sets the primary Parity Error Detected bit.
Configuration
Register or
• Writes the data normally.
CSR Write
1 | — • Sets the primary Parity Error Detected bit.
• Asserts p_perr_l.
Configuration
— |
Register or Returns read data normally.
—
CSR Read
21555 Non-Transparent PCI-to-PCI Bridge User Manual