Intel 21555 User Manual page 163

Table 79. Chip Status Register
All of the following conditions can cause the assertion of p_serr_l or s_serr_l if the corresponding SERR#
enable bit is set and the disable bit for this condition is not set.
• Primary byte offset: D1:D0h
• Secondary byte offset: D1:D0h
Bit
3
7:4
8
9
10
11
15:12
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Name R/W Description
This bit is set to a 1 and p_serr_l is conditionally asserted when the
Downstream
21555 discards a downstream posted write transaction after receiving
Posted Write
2
R/W1TC
Data
not be disabled).
Discarded
Reset value is 0
Reserved R Reserved. Returns 0 when read.
Upstream
This bit is set to a 1 and s_serr_l is conditionally asserted when the
Delayed
secondary master timeout counter expires and an upstream delayed
Transaction R/W1TC
transaction completion is discarded from the 21555's queues.
Master
Reset value is 0
-
Time out
This bit is set to a 1 and s_serr_l is conditionally asserted when the
Upstream
21555 discards an upstream delayed read transaction request after
Delayed
receiving 2
Read R/W1TC
counters must not be disabled).
Transaction
Discarded
Reset value is 0
This bit is set to a 1 and s_serr_l is conditionally asserted when the
Upstream
21555 discards an upstream delayed write transaction request after
Delayed
receiving 2
Write R/W1TC
counters must not be disabled).
Transaction
Discarded
Reset value is 0
This bit is set to a 1 and s_serr_l is conditionally asserted when the
Upstream
21555 discards an upstream posted write transaction after receiving
Posted Write
2
R/W1TC
Data
be disabled).
Discarded
Reset value is 0
Reserved R Reserved. Returns 0 when read.
24
target retries from the secondary bus target (Retry counters must
24
target retries from the primary bus target (Retry
24
target retries from the primary bus target (Retry
24
target retries from the primary bus target (Retry counters must not
List of Registers
163