Intel 21555 User Manual page 189

Table 124. CompactPCI Hot
Offsets
Primary byte
Secondary byte
Bit Name
7:0 HS ECP ID
HS NXT
7:0
PTR
Table 125. CompactPCI Hot
• Primary byte offset: EF:EEh
• Secondary byte offset: EF:EEh
Bit Name
0 Reserved
1 ENUM_MASK
2 Reserved
3 LED On/Off (LOO)
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Swap Capability Identifier and Next Pointer Register
-
HS ECP ID
ECh
ECh
R/W Description
Enhanced capabilities ID. Reads only as 06h to indicate that these are
R
CompactPCI Hot
Pointer to next set of ECP registers. Reads only as 0 to indicate that
R
these are the last ECP registers in this list.
- Swap Control Register (Sheet 1 of 2)
R/W Description
R Reserved. Read only as 0.
ENUM# Interrupt Mask.
• When 0, the 21555 asserts p_enum_l when an insertion or removal
event occurs.
R/W
• When 1, the 21555 does not assert p_enum_l.
• Reset value is 0
R Reserved. Read only as 0.
LED On/Off (LOO) Control. Allows software control of the l_stat pin and
therefore the state of the LED.
• When 0, the 21555 tristates l_stat. When REM STAT is low, the
LED is off when the ejector handle is closed and on when the
R/W
ejector handle is open. When REM STAT is high, l_stat is not
tristated but continues to be driven by the 21555 (LED is off).
• When 1, the 21555 drives l_stat high and the LED is forced on.
• Reset value is 0
HS Next Pointer
EDh
EDh
-
Swap registers.
List of Registers
189