Intel 21555 User Manual page 124

List of Registers
Table 32. Configuration Space Address Register (Sheet 3 of 5)
Byte
Offset
(Hex)
7D (P)
3D (S)
7E (P)
3E (S)
7F (P)
3F (S)
83:80
87:84
8B:88
8F:8C
90
91
92:93
9B:98
A7:A4
97:94
9F:9C
A3:A0
AB:A8
AF:AC
B7:B4
BB:B8
B3:B0
BF:BC
C3:C0
124
Register Name
Primary and Secondary Interrupt
Pin Registers, page 155
Primary and Secondary Minimum
Grant Registers, page 155
Primary and Secondary
Maximum Latency Registers,
page 155
Downstream and Upstream
Configuration Address Registers,
page 141
Downstream Configuration Data
and Upstream Configuration
Data Registers, page 142
Downstream and Upstream
Configuration Address Registers,
page 141
Downstream Configuration Data
and Upstream Configuration
Data Registers, page 142
Configuration Own Bits Register,
page 142
Configuration CSR, page 143
Downstream I/O or Memory 1
and Upstream I/O or Memory 0
Translated Base Register, page
136
Downstream Memory 0, 2, 3, and
Upstream Memory 1 Translated
Base Register, page 137
Downstream Memory 0, 2, 3, and
Upstream Memory 1 Setup
Registers, page 139
Downstream Memory 2 Setup
Downstream Memory 3 Setup
Downstream I/O or Memory 1
and Upstream I/O or Memory 0
Setup Registers, page 138
Upper 32 Bits Downstream
Memory 3 Setup Register, page
140
Primary Expansion ROM Setup
Register, page 176
Reset Value
Preload
(Hex)
00 —
00 Y
00 Y
Indeterminate —
Indeterminate —
Indeterminate —
Indeterminate —
00 —
00 —
0000 —
Indeterminate —
Indeterminate —
Indeterminate —
Indeterminate —
Indeterminate —
Indeterminate —
FFFFF000 Y
00000000 Y
00000000 Y
00000000 Y
00000000 Y
00000000 Y
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Write Read
Access Access
N Y
N Y
N Y
Primary Y
Primary Primary
Secondary Y
Second
Secondary
ary
Primary
N Read-0-
to- set
Second
ary
N
Read-0-
to- set
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
Secondary Y
Secondary Y
Secondary Y
Secondary Y
Secondary Y
Secondary Y