Intel 21555 User Manual page 29

Table 8. Secondary PCI Bus Interface Signals (Sheet 2 of 2)
Signal Name
s_par
s_stop_l
s_trdy_l
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Type Description
Secondary PCI interface parity. Signal s_par carries the even parity of the 36 bits of
s_ad[31:0] and s_cbe_l[3:0] for both address and data phases. Signal s_par is
driven by the same agent that drives the address (for address parity) or the data (for
data parity). Signal s_par contains valid parity one clock cycle after the address is
valid (indicated by assertion of s_frame_l), or one clock cycle after the data is valid
(indicated by assertion of s_irdy_l for write transactions and s_trdy_l for read
TS
transactions). Signal s_par is tristated one clock cycle after the s_ad lines are
tristated. The device receiving data samples s_par as an input to check for possible
parity errors.
When the secondary PCI bus is idle, the 21555 drives s_par to a valid logic level
when its secondary bus grant is asserted (one clock cycle after the s_ad bus is
parked).
Secondary PCI interface STOP#. Signal s_stop_l is driven by the target of a
transaction, indicating that the target is requesting the initiator to stop the
transaction on the secondary bus.
When s_stop_l is asserted in conjunction with s_trdy_l and s_devsel_l assertion,
a disconnect with data transfer is being signaled.
When s_stop_l and s_devsel_l are asserted, but s_trdy_l is deasserted, a target
STS disconnect without data transfer is being signaled. When this occurs on the first data
phase, that is, no data is transferred during the transaction, this is referred to as a
target retry.
When s_stop_l is asserted and s_devsel_l is deasserted, the target is signaling a
target abort.
Upon completion of a transaction, s_stop_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.
Secondary PCI interface TRDY#. Signal s_trdy_l is driven by the target of a
transaction to indicate the target's ability to complete the current data phase on the
secondary PCI bus.
During a write transaction, assertion of s_trdy_l indicates that the target is able to
accept write data for the current data phase.
STS
During a read transaction, assertion of s_trdy_l indicates that the target is driving
valid read data on the s_ad bus. Once asserted during a given data phase, s_trdy_l
is not deasserted until the data phase completes.
Upon completion of a transaction, s_trdy_l is driven to a deasserted state for one
clock cycle and is then sustained by an external pull-up resistor.
Signal Descriptions
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