Preface - Intel 21555 User Manual

Preface

A brief description of the contents of this manual follows.
Chapter 1, "Preface"
Chapter 2, "Introduction"
Chapter 3, "Signal Descriptions"
Chapter 4, "Address Decoding"
Chapter 5, "PCI Bus Transactions"
Chapter 6, "Initialization
Requirements"
Chapter 7, "Clocking"
Chapter 8, "Parallel ROM
Interface"
Chapter 9, "Serial ROM Interface"
Chapter 10, "Arbitration"
Chapter 11, "Interrupt and
Scratchpad Registers"
Chapter 12, "Error Handling"
Chapter 13, "JTAG Test Port"
Chapter 14, "I2O Support"
Chapter 15, "VPD Support"
Chapter 16, "List of Registers"
Appendix A, "Acronyms"
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Provides information about the contents and organization of this book.
Provides an overview of the 21555 functionality and architecture.
Describes PCI signal pins grouped by function.
Contains details about how addresses are decoded.
Describes how the 21555 implements the theory of operation about PCI
transactions.
Describes the reset operation and initialization requirements.
Describes 21555 clocking support.
Describes the 21555 Parallel ROM Interface.
Describes the 21555 Serial ROM Interface.
Explains how 21555 implements primary and secondary PCI bus
arbitration.
Describes interrupt support and scratchpad registers.
Describes parity error responses and system error reporting.
Explains the implementation of JTAG test port.
Explains how the 21555 implements an I20 messaging unit.
Describes Vital Product Data support through SROM interface.
This chapter contains all of the 21555 register information and contains
a register summary.
Definition of terms used in this book.
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