Intel 21555 User Manual page 5

9.2 SROMSROM Preload Operation ........................................................................................91
9.3 SROM Configuration Data Preload Format ........................................................................92
9.4 SROM Operation by CSR Access ......................................................................................92
10 Arbitration ......................................................................................................................................97
10.1 Primary PCI Bus Arbitration Signals ...................................................................................97
10.2 Secondary PCI Bus Arbitration Signals ..............................................................................97
10.3 Primary PCI Bus Arbitration................................................................................................98
10.4 Secondary PCI Bus Arbitration ...........................................................................................98
10.4.1 Secondary Bus Arbitration Using the Internal Arbiter ............................................98
10.4.2 Secondary Bus Arbitration Using an External Arbiter ..........................................100
11 Interrupt and Scratchpad Registers .............................................................................................101
11.1 Primary and Secondary PCI Bus Interrupt Signals ...........................................................101
11.2 Interrupt Support...............................................................................................................101
11.3 Doorbell Interrupts ............................................................................................................103
11.4 Scratchpad Registers .......................................................................................................103
12 Error Handling .............................................................................................................................105
12.1 Error Signals .....................................................................................................................105
12.1.1 Primary PCI Bus Error Signals.............................................................................105
12.1.2 Secondary PCI Bus Error Signals........................................................................106
12.2 Parity Errors ......................................................................................................................107
12.3 System Error (SERR#) Reporting .....................................................................................110
13 JTAG Test Port............................................................................................................................111
13.1 JTAG Signals ....................................................................................................................111
13.2 Test Access Port Controller ..............................................................................................112
13.2.1 Initialization ..........................................................................................................112
14 I2O Support .................................................................................................................................113
14.1 Inbound Message Passing ...............................................................................................113
14.2 Outbound Message Passing.............................................................................................115
14.3 Notes ................................................................................................................................116
15 VPD Support................................................................................................................................119
15.1 Reading VPD Information .................................................................................................119
15.2 Writing VPD Information ...................................................................................................120
16 List of Registers ...........................................................................................................................121
16.1 Register Summary ............................................................................................................121
16.2 Configuration Registers ....................................................................................................122
16.3 Control and Status Registers ............................................................................................126
16.4 Address Decoding ............................................................................................................130
16.4.1 Primary and Secondary Address ........................................................................130
16.4.2 Configuration Transaction Generation Registers.................................................140
16.5 PCI Registers....................................................................................................................147
16.5.1 Configuration Registers .......................................................................................147
16.5.2 Primary and Secondary Command Registers......................................................149
16.5.3 Device-Specific Control and Status Registers .....................................................156
16.6 I2O Registers ....................................................................................................................165
21555 Non-Transparent PCI-to-PCI Bridge User Manual
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