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Table 39. Upper 32 Bits Downstream Memory 3 Bar
• Primary byte offset: 27:24h
• Secondary byte offset: 67:64h
Bit
31:0
Table 40. Upstream Memory 2 Bar
• Primary byte offset: 63:60h
• Secondary byte offset: 23:20h
This register defines the memory range for upstream forwarding of transactions using lookup table based
address translation. All other BARs use direct offset address translation when forwarding transactions.
The size of this register is programmed or disabled by setting the page size in the Chip Control 1 configuration
register.
Bit
0
2:1
3
13:4
31:14
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Name
R/W
Base Address
R/W
Name
R/W
Space Indicator
R
Type
R
Prefetchable
R
—
R
Base Address
R/W
Description
This register defines the upper 32 bits of a memory range for
downstream forwarding of memory transactions. The lower 32 bits
are contained in the Downstream Memory 3 BAR. These bits are
used to indicate the size of the requested address range and to set
the base address of the range. The value of each bit in the Upper 32
Bits Downstream Memory 3 Setup register determines the function of
the corresponding bit in this register.
• When a bit in the setup register is 0, the same bit in this register
-
is a read
only bit and always return 0 when read.
• When a bit in the setup register is one (1), the same bit in this
register is writable and returns the value last written when read.
This BAR is disabled when bit [31] of the Upper 32 Bits Downstream
Memory 3 BAR is 0. The minimum size for this address range is 4 K.
63
The maximum size is 2
bytes.
• Reset value is Read only as 0 (range is disabled).
Description
Reads only as 0 to indicate that memory space is requested.
Indicates size and location of this address space. Reads as 00 to
indicate that this space can be mapped anywhere in 32
When this address range is enabled, read only as 1h to indicate
prefetchable memory. Page entries also may be individually
designated as prefetchable or nonprefetchable, where a
nonprefetchable entry overrides this prefetchable bit.
Read Only. Returns 0 when read.
These bits are used to indicate the size of the requested address
range and to set the base address of the memory range for
upstream forwarding using lookup table based address translation.
The size of this window is a function of the page size, and can vary
from 16 KB to 4 MB increasing by powers of two. The number of
writable bits is dependent on the window size, and varies from
[31:14] for a 16 KB window to [31:28] for a 256 MB window.
Reset value is This address range is disabled (reads only as 0).
List of Registers
-
bit memory.
135
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