Primary And Secondary Command Registers - Intel 21555 User Manual

16.5.2

Primary and Secondary Command Registers

The register types in this section have separate registers for the primary and secondary interfaces. However, the
register description is given once, and applies to both the primary and secondary configuration registers. The
primary register controls behavior on the primary interface only, and the secondary register controls behavior on the
secondary interface only.
Table 61. Primary and Secondary Command Registers (Sheet 1 of 2)
Offsets
Primary byte
Secondary byte
Bit
0
1
2
3
4
5
6
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Primary Command
05:04h
45:44h
Name R/W Description
Controls response to I/O transactions on the corresponding interface.
• When 0, the 21555 does not respond to I/O transactions.
I/O Space
R/W
Enable
• When 1, the 21555 response to I/O transactions is enabled.
• Reset value is 0
Controls response to memory transactions on the corresponding
interface.
Memory
• When 0, the 21555 does not respond to memory transactions.
R/W
Space Enable
• When 1, the 21555 response to memory transactions is enabled.
• Reset value is 0.
Controls 21555's ability to initiate memory and I/O transactions on the
corresponding interface. Initiation of configuration transactions is not
affected.
Master Enable R/W
• When 0, the 21555 does not initiate memory or I/O transactions.
• When 1, the 21555 is enabled to operate as an initiator.
• Reset value is 0.
Special Cycle The 21555 ignores special cycle transactions, so this bit is read only and
R
Enable returns 0.
This bit controls the ability of the 21555 to generate Memory Write and
Invalidate (MWI) bus commands as a master on the corresponding
interface.
Memory Write
• When 0, Disables use of MWI bus commands (uses Memory Write
and Invalidate R/W
Enable
• When 1, Enables use of MWI bus commands.
• Reset value is 0
VGA Snoop Reads only as 0 to indicate the 21555 does not respond to VGA palette
R
Enable writes.
Controls the response of the 21555 when a parity error is detected on the
corresponding interface.
• When 0, the 21555 does not assert PERR#, nor does it set the Data
Parity Error
R/W
Response
• When 1, the 21555 drives PERR# and conditionally sets the Data
• Reset value is 0.
commands instead).
Parity Reported bit in the appropriate Primary or Secondary Status
registers. The 21555 does not report address parity errors by
asserting SERR#.
Parity Reported bit in the Primary or Secondary Status register when
a data parity error is detected. The 21555 allows SERR# assertion
when address parity errors are detected.
List of Registers
Secondary Command
45:44h
05:04h
149