Xerox 550 Reference Manual page 68

SH
SUBTRACT HALFWORD
(Halfword index alignment)
SUBTRACT HALFWORD extends the sign of the effective
halfword 16 bit positions to the left (to form a 32-bit word
in which bit positions 0-15 contain the sign of the effec-
tive halfword), forms the two's cQmplement of the resulting
word, adds the complemented word to the contents of reg-
ister R, and loads the sum into register R.
Affected: (R), CC Trap: Fixed-point overflow
-EH + (R)-R
SE
Condition code settings:
2 3 4 Resu It in R
o
0 Zero
- - 0 Negative
o
Positive
- 0 No fixed-point overflow
Fixed-point overflow
o -
No carry from bit position 0
- Carry from bit position 0
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.
SW
SUBTRACT WORD
(Word index alignment)
o
1 314567891011121314151617181912021222324252627128293031
SUBTRACT WORD forms the two's complement of the effec-
tive word, adds that complement to the contents of regis-
ter R, and loads the sum into register R.
Affected: (R), CC Trap: Fixed-point overflow
-EW + (R)-R
Condition code settings:
2 3 4 Resu It in R
o
0 Zero
o
Negative
2 3 4 Result in R
o
Positive
- 0 - - No fixed-point overflow
- - Fixed-point overflow
o - - -
No carry from bit position 0
Carry from bit position 0
If
CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.
so
SUBTRACT DOUBLEWORD
(Doubleword index alignment)
'SUBTRACT DOUBLEWORD forms the 64-bit two's comple-
ment of the effective doubleword, adds the complemented
doubleword to the contents of registers Rand Ru1 (treated
as a single, 64-bit register), loads the 32 low-order bits of
the sum into register Ru 1 and loads the 32 hi gh -order bits
of the sum into register R.
Affected: (R), (Rul), CC
-ED
+
(R, Ru1) - R, Ru1
Condition code settings:
2 3 4 Result in R, Ru1
o
0 Zero
- - 0
Negative
o
Positive
Trap: Fixed-point overflow,
instruction exception
- 0
- No fixed-point overflow
Fixed-point overflow
o -
- No carry from bit position 0
- Carry from bit position 0
If
CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X ' 43
1
after the re-
sult is loaded into registers Rand Ru1; otherwise, the BP
executes the next instruction in sequence.
The R field of the SD instruction must be an even value for
proper operation of the instruction; if the R field of SD is
an odd value, the instruction traps to location X'4D',
instruction exception trap; the contents in register R remain
unchanged.
Fixed-Point Arithmetic Instructions 61