Fixed-Point Overflow Trap - Xerox 550 Reference Manual

Operation
Instruction
Mnemonic Code
Push Multiple
PSM X'OB '
Pull Multiple
PLM
X'OA'
Modify Stack Pointer MSP
X' 13 1
During the execution of any stack-manipulating instruction
(see Chapter 3, II Push-down Instructi ons II), the stack is
either pushed (words added to stack) or pulled (words re-
moved from stack). In either case, the space (S) and words
0N)
fields of the stack pointer doubleword are tested prior
to moving any words.
If
execution of the instruction would
cause the space (S) field to become les·s than 0 or greater
than 2 15 _1, the instruction is aborted with memory and
registers unchanged.
If
TS (bit 32) of the stack pointer
doubleword is set to 0, the basic processor traps to location
X'421.
If
TS is set to 1, the trap is inhibited and the basic
processor processes the next instruction.
If
execution of
the instruction would cause the words
0N)
field to become
less than 0 or greater than 2 15 _1, the instruction is aborted
with memory and registers unchanged.
If
TW (bit 48) of
the stack pointer doubleword is set to 0, the basic processor
traps to location X'421.
If
the TW is set to 1, the trap is
inhibited and the basic processor processes the next instruc-
tion.
If
trapping is inhibited, CC 1 or CC3 is set to 1 to
indicate the reason for aborting the instruction. The stack
pointer doubleword, memory, and registers are modified
only if the instruction is successfully executed.
If a push-down instruction traps, the execution of XPSD or
PSS in trap location X ' 42 1 is as follows:
1. Store the current PSWs. The condition codes that are
stored are those that existed prior to execution of the
aborted push-down instruction.
2. Store general registers if PSS.
3. Load the new PSWs. The condition code and instruc-
tion address portions of the PSWs remain at the value
loaded from memory.
FIXED-POINT OVERFLOW TRAP
Overflow can occur for any of the following instructions:
Instruction
Load Absolute Word
Load Absolute Doubleword
Mnemonic
LAW
LAD
Operation
Code
X' 1B '
Operation
Instruction
Mnemonic Code
Load Complement Word LCW X ' 3A '
Load Comp lement Doub
I
eword LCD X ' 1A '
Add Halfword AH
X ' 50 '
Subtract Halfword SH
X ' 58
1
Divide Halfword
DH X ' 56
1
Add Immediate AI X ' 20 '
Add Word AW X ' 30 '
Subtract Word SW X ' 38
1
Divide Word DW
X ' 36 1
Add Doubleword AD
X'10 '
Subtract Doub leword SD
X ' 18 1
Modify and Test Halfword MTH
X ' 53 1
Modify and Test Word MTW
X '33 1
Add Word to Memory AWM
X ' 66 1
Except for the instructions DIVIDE HALFWORD (DH) and
DIVIDE WORD (OW), instruction execution is allowed to
proceed to completion. CC2 is set to 1 and CC3 and CC4
represent the actual result (0, -, or
+)
after overflow.
If the fixed-point arithmetic trap mask (bit 11 of PSWs) is
a 1, the basic processor traps to location X 143 1 instead of
executing the next instruction in sequence.
For DWand DH, the instruction execution is aborted with-
out changing any register, and CC2 is set to 1; CC 1, CC3,
and CC4 remain unchanged from their values at the end of
the instruction immediately prior to the DW or DH. If the
fixed-point arithmetic trap mask is a 1, the basic processor
traps to location X ' 43 1 instead of executing the next instruc-
tion in sequence.
The execution of X PSD or PSS in trap location X 143 1 is as
follows:
1. Store the current PSWs. (Store genera
I
registers if PSS.)
If
the instruction trapped was any instruction other than
DW or DH, the stored condition code is interpreted as
follows:
CC 1 t CC2 CC3 CC4 Meaning
_tt 0 0 Result after overflow is zero.
o
o
Result after overflow is
negative.
Result after overflow is
positive.
tcc 1 remains unchanged for instructions LCW, LAW, LCD,
and LAD.
tt A hyphen indicates that the condition code bits are not af-
fected by the condition given under the "Meaning
II
heading.
Trap System 41