Programmed Trap; Call Instruction Trap; Hardware Error Trap; Instruction Exception Trap - Xerox 550 Reference Manual

PROGRAMMED TRAP
The programmed trap occurs at instruction interruptible
point. It is set by a WRITE DIRECT 0ND). See Chapter 3.
The basic processor traps to location X'47'.
CALL INSTRUCTION TRAP
The four CALL instructions (CAll, CAL2, CAL3, and CAL4)
cause the basic processor to trap tp location X'48' (for
CAll), X'49' (for CAL2), X'4A' (for CAL3), or X'4B' (for
CAL4). Execution of the XPSD or PSS instruction in the
trap location is as follows:
1.
Store the current PSWs. The stored condition code bits
are those that existed prior to the CALL instruction.
2. Store the general registers in PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
a. The R Field of the CALL instruction is logically
ORed with the condition code register as loaded
from memory.
b.
If
bit 9 (AI) of XPSD or PSS contains a 1, the R
field of the CALL instruction is added to the pro-
gram counter. If AI contains a 0, the program
counter remains unchanged from the value loaded
from memory.
Note: Return from a CALL trap will be to the trapping
i nstructi on
+
1.
HARDWARE ERROR TRAP
A hardware error trap occurs when either'a parity or a se-
quence check fault error is detected by a memory unit, basic
processor, or any processor communicating with the basic
processor, resulting in a basic processor trap to location
X'4C'. The Trap Condition Code bits (TCCs) are set to
X'OOOl' for all hardware fault conditions except general
register and control register parity errors, where the TCCs
are set to X'OOOQ'.
To determine which of the possible detectable errors is re-
sponsible for the hardware error trap, the fault status reg-
isters of the various processors in the system must be polled
with either the POLP or POLR instruction; the memoris
status register must be read with the LMS instruction. The
fault status register bit settings for processors and interfaces
are given in Appendix C, Table C-1. The fault status reg-
ister bit settings for the memory unit are given in Ap-
pendix C, Table C-2.
If the basic processor detects or receives a report of a hard-
ware error, it attempts automatic retry of the current in-
struction. If retry is unsuccessful, the basic processor traps
to location X'4C'.
If
retry is successful, the basic processor
resumes execution of the next instruction in the program,
the Processor Fault Interrupt (PFI) and the "successful in-
struction retry" bit (bit position 11) in the Basic Processor
Fault Status Register are set to 1. There is automatic in-
struction retry only for hardware errors that would otherwise
result in a basic processor trap to location X'4C'. Auto-
matic instruction retry is inhibited if:
1. The current instruction is being executed as a trap or
interrupt instruction;
2. The Register Altered bit (bit position 60) of the cur-
rent PSWs is set to 1 at the time of detection of the
hardware error; or
3. The Retry Inhibit bit (bit position 0) in the basic pro-
cessor control register is set to 1.
INSTRUCTION EXCEPTION TRAP
The instruction exception trap occurs whenever the basic
processor detects a set of operati ons that are ca
II
ed for in
an instruction but cannot be executed because of either a
hardware restri ction or a previous event.
The different conditions that cause the instruction exception
trap are:
1.
A processor-detected fault that occurs during the ex-
ecution of an interrupt or trap entry sequence. An
interrupt or trap entry sequence is defined as the se-
quence of events that consists of: (a) initiating an
interrupt or trap; (b) accessing the instruction in the
interrupt or trap location; and (c) executing that in-
struction, including the exchange of the program
status words, if required. Note that instructions ex-
ecuted as a result of the interrupt or trap location are
not considered part of the entry sequence.
2.
An illegal instruction is found in the trap (not XPSD or
PSS) or interrupt (not XPSD, PSS, MTB, MTH, MTW) lo-
cation when executing a trap or interrupt sequence.
3. Bit positions 12-14 of the MOVE TO MEMORY CON-
TROL (MMC) instruction are interpreted as an illegal
T rap System 43