Xerox 550 Reference Manual page 9

• Extensive instruction set that includes:
• Byte, halfword, word, and doubleword operations.
• Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
normal instruction format.
• Multiple register operations.
• Fixed-point integer arithmetic operations in half-
word, word,· and doubleword modes.
• Immediate operand instructions.
• Floating-point hardware operations in short and
long formats with significance, zero, and normal-
ization control and checking, all under full pro-
gram control.
• Full complement of logical operations (AND, OR,
exclusive OR).
• Comparison operations, including compare between
limits (with limits in memory or in registers).
• Call instructions that permit up to 64 dynamically
variable, user-defined instructions, and allow a
program access to operating system functions with-
out operating system intervention.
• Push-down stack operations (hardware imple-
mented) of single or multiple words, with auto-
matic limit checking, for dynamic space alloca-
tion, subroutine communication, and recursive
routi ne capabi
Ii
ty.
• Automatic conversion operations, including binary/
BCD and any other weighted-number systems.
• Analyze instruction that facilitates effective
address computati on.
• Interpret instruction that increases speed of inter-
pretive programs.
• Shift operations (left and right) of word or double-
word, including logical, circular, arithmetic,
searching shift, and floating-point modes.
• Built-in reliability and maintainability features that
include:
• Extensive error logging. When a fault is detected,
system status and fault information
ale available
for program retrieval and logging for subsequent
analysis.
• Full parity checking on all data and addresses
communicated in either direction on buses be-
tween memory units and processors, providing fault
2
General Characteristics
detection and location capability to permit the
operati ng system or diagnostic program to quickly
determine a faulty unit.
• Address stop feature that permits operator or main-
tenance personnel to:
Stop on any instruction address.
Stop on any memory reference address.
Stop when any word in a selected page of
memory is referenced.
• Traps that provide for detection of a variety of
fault conditions, designed to enable a high degree
of system recoverabi
I
i ty.
• Partitioning features that enable system recon-
figuration via a centralized Configuration Con-
trol Panel. Units may be partitioned from the
system by selectively disabling them from buses
(assuming other system facilities can handle the
additional load). Thus, faulty units, processors,
devices, or an alternate system can be isolated
from the operational system to enable diagnosis
or repair while the primary system continues
operation.
• Independently operating I/o system with the following
features:
• Direct input/output (READ DIRECT, W.UTE DIRECT
instructions) for transfer of 32-bit words between
the specified general register and an external de-
vice; a 16-bit address is transferred for selection
and control purposes; and each transfer is under
direct program control.
• Up to five independent I/O processor clusters (re-
stricted only by the maximum number of 6 ports).
• Multiplexor I/O processors (MIOPs) (up to 3 per
I/O
ciuster), each providing for simuitaneous op-
eration of up to 16 devices per processor.
• Data chaining for gather-read and scatter-write
operati ons.
• Command chaining for multiple record operations.
• Write lock protect feature within memory unit
for positive protection from all processors storing
into memory.
.. Comprehensive
modular
software that is program com-
patible with Sigma 5-9 computers:
• Expands in capability and speed as system grows.
• Operati ng system: Control Program Real-Time
(CP-R).