Xerox 550 Reference Manual page 30

Real-extended addressing is specified when PSWs bit
location 9 contains zero and PSWs bit location 61 contains
one. In real-extended addressing, the 17-bit reference
address in the instruction word is expanded to a 20-bit ref-
erence address by the appendage of 3 bit positions to the
left of the reference address (see Figure 8). If indexing or
indirect addressing are not specified in the instruction,
these 3 bit positions contain zeros. Otherwise, address
calculations are performed in this manner: If indexing is
specified (X field in the instructi-on contains a value other
than zero), the contents of the specified index register are
properly al igned with respect to the 17-bit reference ad-
dress according to the general
alignm~nt
rules. Arithmetic
on the aligned quantities then takes place using the full
32-bit contents of the index register. The final result is
truncated 3 bits to the left of the original 17-bit ref-
erence address, these 3 bi ts having been acqui red from
the index register plus any carry resulting from the addition
Instruction in memory:
information used by address
generator:
Byte operation indexing alignment:
Indexed
not indexed
Halfword operation indexing alignment:
Word operation indexing al ignment:
Shift operation indexing alignment:
Doubleword operation indexing alignment:
20-bit effective address:
of the 17-bit reference address with the index register
contents,
If the instruction specifies indirect addressing (bit position 0
contains one), the 17 bit reference address is used to ac-
cess an indirect word in memory. The low-order 20 bits of
the indirect word then replace the 17-bit reference address
from the instruction.
If indexing is also specified, the
appropriate alignment of the 32-bit contents of the index
register is then made and the addition operation performed.
The result is truncated to the left of the 20-bit operand ob-
tained from the indirect address word.
In real-extended addressing, 20-bit address calculations
actually encompass 22-, 21-, 20-, and 19-bitcalculations,
respectively, for byte, halfword, word, and doubleword
alignments (see Figures 8 and 9).
I IIII
22-bii displacement ;alue
Figure 8. Index Displacement Alignment (Real-Extended Addressing)
Main Memory 23