Trap Condition Code; Nonallowed Operation Trap - Xerox 550 Reference Manual

a zero, the trap is not allowed to occur. AM can be
masked by operator intervention, or by execution of
the XPSD, PSS, PLS, or LPSD privi leged instructions.
3. The floating-point significance check trap is masked
by a combination of the floating significance (FS),
floating zero (FZ), and floating normalize (FN) mode
control bits in the PSWs (see IIFloating-Point Arithme-
tic Fault Trapll, later in this chapter). FS, FZ, and
FN can be set or cleared by'the execution of any of
the following instructions:
LOAD CONDITIONS AND FLOATING CON-
TROL (LCF)
LOAD CONDITIONS AND FLOATING CON-
TROL IMMEDIATE (LCFI)
EXCHANGE PROGRAM STATUS WORDS (XPSD)
LOAD PROGRAM STATUS WORDS (LPSD)
PUSH STATUS (PSS)
PULL STATUS (PLS)
TRAP CONDITION CODE
For the push-down stack limit trap, fixed-point overflow
trap, floating-point fault trap, and decimal fault trap, the
normal condition code register (CC1-CC4) is loaded with
more detai led information about the trap condition just
before the trap occurs. These condition codes are saved as
part of the old program status words when the XPSD or PSS
instruction is executed in response to the trap.
For the nonallowed operation trap, watchdog timer runout
trap, hardware error trap, instruction exception trap, and
CALL trap, a special register (trap condition codes TCC1-
TCC4) is loaded just before the trap occurs. When the
XPSD or PSS instruction is executed in response to the trap,
this register is added to the new program address if bit 9
(MM) contains a one; TCC1-TCC4 are also logically ORed
with the condition code bits (CC 1-CC4) of the new PSWs
when loading CC1-CC4. See also IIInstruction Exception
Trap" later in this chapter for more information on the trap
condition code.
NONALLOWED OPERATION TRAP
The attempt to perform a nonallowed operation always
causes the basi c processor to abort the instruction being
executed when the nonallowed operation is detected and
to immediately execute the XPSD or PSS instruction in
trap location X'40'. A nonallowed operation cannot be
masked.
NONEXISTENT INSTRUCTION
Any instruction that is not standard is defined as nonexist-
ent. This includes immediate operand instructions that
specify indirect addressing (a one in bit 0 of the instruction).
If a nonexistent instruction is detected, the basic processor
traps to location X 140' when the nonexistent instruction is
decoded. No general registers or memory locations are
changed; the PSWs point to the instruction trapped. With
respect to the condition code and instruction address fields
of the program status words, the operation of the XPSD or
PSS in location X ' 40 ' is as follows:
1. Store the current PSWs. The condition codes stored are
those that existed at the end of the last instruction
prior to the nonexistent instruction.
2. Store the 16 general registers of the current register
block if instruction in trap location is a PSS.
3. Load the new PSWs.
4. Modify the new PSWs.
o. Set CC 1 to one. The other condition code bits
remain unchanged from the vaiues ioooea from
memory.
b. If bit position 9 (AI) of the XPSD or PSS instruc-
tion contai ns a one, the program counter is incre-
mented by eight. If AI contains a zero, the
program counter remains unchanged from the value
loaded from memory.
NONEXISTENT MEMORY ADDRESS
Any attempt to access a nonexistent memory address causes
a trap to location X'40 ' at the time of the request for mem-
ory service. A nonexistent memory address condition is
detected when an actual address is presented to the memory
system. If the basic processor is in the map mode, the
program address wi
1/
already have been modified by the
memory map to generate an actual (but nonexistent) ad-
dress. (See Table 5 for possible changes to registers and
memory locations later in this chapter.) The operation of
the XPSD or PSS in location X ' 40' is as follows:
1. Store the current PSWs.
2. Store general registers if PSS.
Trap System 39