Wait - Xerox 550 Reference Manual

Table 10. Status Word 1
Field Bits Comments
0 Interleave switch ON
1-3 Memory unit size:
000 8K
001 16K
010· 24K
011 32K
100 40K
101 48K
110
56K
111
64K
4-6 Memory unit number (binary code)
Starting 7
Starting address bit 12
Address
8 Starting address bit 13
9 Starting address bit 14
10 Starting address bit 15
11
Starting address bit 16
12
Starting address bit 17
13 Starting address bit 18
14 Reserved
15-31 Address received, bits 15-31
WAIT
WAIT
(Word index al ignment, privileged)
WAIT causes the basic processor to cease all operations until
an interrupt activation occurs, or until the operator puts
the basic processor in the IDLE mode and then back to RUN
(see Chapter 5). The instruction address portion of the PSWs
is updated before the basic processor begins waiting; there-
fore, while it is waiting, the INSTRUCTION ADDRESS indi-
cators contain the virtual address of the next location in
ascending sequence after WAIT and the contents in the next
location are displayed in the DISPLAY indicators on the
processor control console. If any input/output operations
are being performed when WAIT is executed, the operations
proceed to their normal termination.
When an interrupt activation occurs while the basic pro-
cessor is waiting, it processes the interrupt-servicing routine.
Normally, the interrupt-servicing routine begins with an
XPSD instruction in the interrupt location, and ends with
an LPSD instruction at the end of the routine. After the
LPSD instruction is executed, the next instruction to be ex-
ecuted in the interrupted program is the next instruction in
sequence after the WAIT instruction. If the interrupt is to a
single-instruction interrupt location, the instruction in the
interrupt location is executed and then instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction. When the basic processor execution mode
is changed from RUN mode to IDLE mode and back to RUN
while the basic processor is waiting, instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction.
Affected: PC
If WAIT is indirectly addressed and the indirect reference
address is nonexistent, the nonallowed operation trap to
location X'40' will not occur. The effective virtual address
of the WAIT instruction, however, is not used as a memory
reference (thus does not affect the norma
I
operation of the
instruction).
RD
READ DIRECT
(Word index alignment, privileged)
The basic processor is capable of directly communicating
with other elements of the system, as well as performing
internal control operations, by means of the READ DIRECT /
WRITE DIRECT (RD/WD) lines. The RD/WD lines consist of
16 address lines, 32 data lines, two condition code lines,
and various control lines that are connected to various basic
processor circuits and to special system equipment.
READ DIRECT causes bits 16 through 31 of the effective
virtual address to be presented to other elements of the sys-
tem on the RD/WD address lines. Bits 16-31 of the effective
virtual address identify a specific elementof the system that
is expected to return information (two condition code bits
plus a maximum of 32 data bits) to the basic processor. The
sign ifi cance and number of data bits returned depend on the
selected element.
If the R field of RD is nonzero, up to
32 bits of the returned data are loaded into general regis-
ter R; however, if the R field of RD is 0, the returned data
is ignored and general register 0 is not changed. Bits CC3
and CC4 of the condition code are set by the addressed
element, regardless of the value of the R field.
Bits 16-19 of the effective virtual address of RD determine
the mode of the RD instruction, as follows:
Bit Position
16 17 18 19
Mode
o
0 0 0 Interna
I
basi c processor control.
0 0 0 Interrupt control.
0 0 0 Xerox testers.
Control Instructions 103