Pls - Xerox 550 Reference Manual

Memory Stack:
(General Register n) - (initial TSA+{n+ 1) where n has
ascending values from 0 through 15.
PSW1 - (initial TSA+25)
PSW2 - (initial TSA+26)
Status Stack Pointer Doubleword:
TSA+1 - TSA unti
I
terminal TSA=initial TSA+28;
Word Count + 1 - Word Count unti
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terminal Word
Count
=
initial Word Count + 28, (if Word Count>
32,767, set bit 48 to 1);
Space Count - 1 - Space Count until terminal Space
Count = initial Space Count - 28 (if Space Count = 0,
Space Count - 1 is indeterminate).
PLS
PULL STATUS (nonaddressing, privi leged)
PULL STATUS, in conjunction with the Status Stack Pointer
Doubleword, may cause one or more of the following func-
tions to be performed: .
1. Selectively load a new environment (PSWs and 16 gen-
eral registers) from the memory stack; or,
2. Selectively load default PSWs from dedicated memory
locations; and,
3. Selectively clear and arm or clear and disarm the
highest priority level currently in the active state.
If the initial Word Count of Status Stack Pointer Doubleword
is equal to or greater than 28, a new environment is
loaded from the memory stack. Twenty eight memory stack
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at a location having an address equal to the initial TSA
(part of the Status Stack Pointer Doubleword). The hard-
ware selects and loads the contents of 20 memory locations
into the general registers and as the PSWs (i.
e.,
the con-
tents of locations having relative addresses of initial TSA-2,
initial TSA-3, and initial TSA-12 through initial TSA-27).
The contents of 10 memory stack locations (having relative
addresses equal to initial TSA, initial TSA-1, and initial
TSA-4 through initial TSA-ll) are ignored.
Portions of the new PSWs are dependent upon the LP flag
(bit 8) of the PLS instruction as well as the interrupt group
inhibit bits of the old PSWs and the PSWs as pulled from
the memory stack.
If
the LP flag is a 1, a new Register
Block Pointer (as pulled from the memory stack) is loaded
as part of the new PSWs. If the LP flag is a 0, the old Reg-
ister Block Pointer is retained as the Register Block Pointer
for the new PSWs. The new interrupt group inhibit bits (CI,
88 Push-Down Instructions (Privileged)
11, EI) are generated by "ORing" the old CI, II, EI bits
with the contents of bits 37, 38, and 39 of the PSWs as
pulled from the memory stack.
The clearing and arming or disarming the highest priority
interrupt level currently active is dependent upon the
coding of the CL and AD flags (bit positions 10 and
11,
respectively) of the PLS instruction. Jf the CL flag is a 0,
the interrupt level is not affected.
If
the CL flag is a 1
and the AD flag is a 0, the interrupt level is set to the dis-
armed state. If the CL flag is a 1 and the AD flag is a 1,
the interrupt level is set to the armed state. Note that if
the interrupt level is to be modified (CL flag is set to a 1),
the instruction may be delayed unti
I
the interrupt system is
available.
Summary description of CL and AD flags and effect on in-
terrupt level and PDF flag follows:
Bit Positions
10 (CL)
o
o
11
(AD)
o
o
Function
No effect upon interrupt level
or PDF flag.
Reset PDF flag
Clear and disarm interrupt level
Clear and arm interrupt level
If
the initial Word Count is zero! default PSWs are loaded
from real memory locations 2 and 3 and the other parameters
of the Status Stack Pointer
Doubleword
are not effective
and no parameters are affected.
Portions of the new PSWs (interrupt inhibit group bits and
the Register Block Pointer) may be
selected
or generated in
the following manner:
If
the LP flag (bit 8) of the PSL instruction is a 1, the new
Register Block Pointer will be as obtained from the default
PSWs.
If
the LP flag is a 0, the Register Block Pointer of
the old PSWs is retained as the Register Block Pointer for
the new PSWs.
The CI, II, and EI bits of the old PSWs are "ORed" with
the contents of bit positions 37, 38, and 39 of the default
PSWs to generate the CI, II, and EI bits of the new PSWs.
Depending upon the coding of the CL and AD flags (bit
positions 10 and 11: respectively) of the PLS instruction;
the highest priority interrupt level currently in the active
state may be modified. If the CL flag is a 0, the interrupt
level is not affected.
If
the CL flag is ') 1 and the AD flag
is a 0, the interrupt level is cleared and placed into the
disarmed state. If the CL flag is a 1 and the AD flag is
a 1, the interrupt level is cleared and placed into the