Bcs; Bcr; Bir; Bdr - Xerox 550 Reference Manual

BCS BRANCH ON CONDITIONS SET
(Word index alignment)
BRANCH ON CONDITIONS SET forms the logical product
(AND) of the R field of the instruction word and the current
condition code.
If the logical product is nonzero, the
branch condition is satisfied and instruction execution pro-
ceeds with the instruction pointed to by the effective ad-
dress of the BCS instruction. However, if the logical prod-
uct is zero, the branch condition is unsatisfi ed and instruc-
tion execution then proceeds with the next instruction in
normal sequence.
Affected: (IA) if CC n R
f
0
If CC n (1)8-11
"10,
EVA 15-31 - IA
If CC n (I)8-11
=
0, IA not affected
If the R field of BCS is 0, the next instruction to be exe-
cuted after BCS is always the next instruction in ascending
sequence, thus effectively producing a "no operation"
instruction.
BCR
BRANCH ON CONDITIONS RESET
(Word index ailgnment)
BRANCH ON CONDITIONS RESET forms the logical prod-
uct (AND) of the R field of the instruction word and the
current condition code. If the logical product is zero, the
branch condition is satisfied and instruction execution then
proceeds with the instruction pointed to by the effective
address of the BCR instruction. However, if the logical
product is nonzero, the branch condition is unsatisfied and
instruction execution then proceeds with the next instruc-
tion in normal sequence.
Affected: (IA) if CC n R
=
0
If CC n (I)8-11
=
0, EVA 15-13 - IA
If CC n (I)8-11
10,
IA not affected
If
the R field of BCR is 0, the next instruction to be exe-
cuted after BCR is always the instruction located at the
effective address of BCR, thus effectively producing a
"branch unconditionally" instruction.
BIR
BRANCH ON INCREMENTING REG ISTER
(Word index alignment)
BRANCH ON INCREMENTING REGISTER computes the
effective virtual address and then increments the contents
of general register R by 1. If the result is a negative value,
the branch condition is satisfied and instruction execution
then proceeds with the instruction pointed to by the effec-
tive address of the BIR instruction. However, if the result
is zero or a positive va lue, the branch condition is not sat-
isfied and instruction execution proceeds with the next in-
struction in normal sequence.
Affected: (R), (IA)
(R) + 1 - R
If (R)O
=
1, EVA 15 _ 31 -IA
If {R)O
=
0, IA not affected
If the branch condition is satisfied and if the effective ad-
dress of BIR is either unavailable to the program (slave or
master-protected mode) for instruction access or is non-
existent, the basic processor aborts execution. of the BIR
instruction and traps to location X'40'. In this case, the
instruction address stored by the XPSD instruction in loca-
tion X'40' is the virtual address of the aborted BIR instruc-
tion. If the basic processor traps because of instruction
access protection, register R will contain the value that
eXisted rust before the BIK execution (I.e., updated instruc-
tion address). If a memory parity error occurs due to the
accessing of the instruction to whi ch the program is branch-
ing, the basic processor aborts execution of the BIR and
traps to location X ' 4C' with register R unchanged.
BOR
BRANCH ON DECREMENTING REGISTER
(Word index alignment)
BRANCH ON DECREMENTING REGISTER computes the
effective virtual address and then decrements the contents
of general register R by 1. If the result is a positive value,
the branch condition is satisfied and instruction execution
then proceeds with the instruction pointed to by the effec-
tive address of the BDR instruction. However, if the result
is zero or a negative value, the branch condition is unsatis-
fied and instruction execution proceeds with the next in-
struction in normal sequence.
Affected: (R), (IA)
(R) - 1 - R
If {R)O
=
0 and {R)1-31
10,
EVA 15 _ 31 - IA
If (R)O
=
1 and (R)
=
0, IA not affected
Execute/Branch Instructions 91