Xerox 550 Reference Manual page 102

XPSD (trap instruction)
An XPSD instruction (in a trap location) executed as a result
of a trap entry operation is called a trap instruction. Ad-
dressing is the same as for the interrupt XPSD (see above).
The following additional operations are performed on the
new program status words if, and only if, the XPSD is being
executed as the result of a nonallowed operation (trap to
location X ' 40 ' ) or a CAll instruction (trap to location X ' 48 I ,
X ' 49', X ' 4A', or X'4B'):
1. Nonallowed operations - the following additional func-
tions are performed when XPSD is being executed as a
result of a trap to location X ' 40':
a. Nonexistent instruction - if the reason for the trap
condition is an attempt to execute a nonexistent
instruction, bit position Oof the new program status
words (CC 1) is set to 1.
Then, if bit 9 (AI) of
XPSD is a 1, bit positions 15-31 of the new pro-
gram status words (next instruction address) are
incremented by 8.
b. Nonexistent memory address - if the reason for the
trap condition is an attempt to access or write into
a nonexistent memory region, bit position 1 of the
new program status words (CC2) is set to 1. Then,
if bit 9 of XPSD is a 1,
the instruction address por-
tion ofthe new program status words is incremented
by
4.
c. Privileged instruction violation - if the reason for
the trap condition is an attempt to execute a priv-
ileged instruction while the basic processor is in
the slave mode, bit position 2 of the new program
status words (CC3) is set to 1. Then, if bit posi-
tion Oof XPSD is 1, the instruction address portion
of the new program status words is incremented by 2.
d.
Memory protection violation - if the reason for the
trap condition is an attempt to read from or write
into a memory region to which the program does
not have proper access, bit position 3 of the new
program status words (CC4) is set to 1.
Then, if
bit 9 of XPSD is a
1,
the instruction address por-
tion of the new program status words is incremented
by 1.
There are certain circumstances under which two
of the above nonal lowed operations can occur
simultaneously. The following operation codes
(including their counterparts) are considered to be
bothnonexistentandprivileged: XIOC I and X'OD'.
If either of these operation codes is used as an in-
struction while the basic processor is in the slave
or master-protected mode, CC 1 and CC3 are both
set to lis; if bit 9 of XPSD is a 1, the instruction
address portion of the new program status words is
incremented by 10. If an attempt is made to access
or write into a memory region that is both nonexist-
ent and prohibited to the program by means of the
memory control feature, CC2 and CC4 are both
set to lis; if bit 9 of XPSD is a 1, the instruction
address of the new program status words is incre-
mented by 5.
2. CALL instructions - the following additional functions
are performed when XPSD is being executed as a re-
sult of a trap to location X'48 1
,
X'49 1
,
X ' 4A', or
X'4B'.
a. The R field of the CALL instruction causing the
trap is logically inclusively ORed into bit posi-
tions 0-3 (CC) of the new PSWs.
b. If bit position 9 of XPSD contains a 1, the R field
of the CALL instruction causing the trap is added
to the instruction address portion of the new PSWs.
3. Watchdog timer, parity error, or instruction exception
trap - the following additional functions are performed
when XPSD is being executed as a result of a trap to
location X'46 I , X'4C', or X'4D', respectively.
a. The contents of TCC 1-4 are logically inclusively
ORed into bit positions 0-3 (CC) of the new PSWs.
b. If bit position 9 of XPSD contains a 1, the contents
of TCC 1-4 are added to the instruction address
portion of the new PSWs.
If bit position 9 of XPSD contains a 0, the instruction ad-
dress portion of the new PSWs always remains at the vaiue
established by the second effective doubleword. Bit posi-
tion 9 of XPSD is effective only if the instruction is being
executed as the result of a nonal lowed operation, CALL
instruction watchdog timer, parity error, or instruction ex-
ception trap. Bit position 9 of XPSD must be coded with a
o
in all other cases; otherwise, the results of the XPSD
instruction are undefined.
The current program status words are stored in the doubl e-
word location pointed to by the effective address of XPSD
in the following form:
Program Status Words
The current program status words (as illustrated above) are
replaced by new program status words as described below.
1. The effective address of XPSD is incremented by 2 so
that it points to the next doubleword location. The
contents of the next doubleword location are referred
to as the second effective doubleword, or ED2.
Control Instructions 95