Table 3.
Summary of Trap Locations (cont.)
Locations
PSWs
Dec.
Hex.
Function
Mask Bit
Time of Occurrence
Trap Condition Code
72
48
CALLl
None
At instruction decode.
Equal to R field of
CALL instruction.
73
49
CALL2
None
At instruction decode.
Equal to R field of
CALL instruction.
74
4A
CALL3
None
At instruction decode.
Equal to R field of
CALL instruction.
75
4B
CALL4
None
At instruction decode.
Equal to R field of
CALL instruction.
76
4C
Hardware error trap
None
At time of basic processor detec-
TCC1, 2, 3
=
0
tion (the PDFt flag wi
II
be set).
TCC4
=
0 if parity
error on general reg-
ister or internal con-
trol regi ster
TCC4
=
1 if other
hardware errors.
77
4D
Instruction exception trap
None
(The PDFt flag wi II be set.)
Set TCC3 if MMC
configuration illegal;
set TCC
=
X'C'
if
trap or interrupt se-
quence with illegal
instruction;
set TCC
=
X'F' if
trap or interrupt se-
quence and processor
detected fau
I
t;
I
set TCC4 if !nvalid
register designation
{odd register on AD,
SD, FAL, FSL, FML,
FDL.
78
4E
Reserved
79
4F
Reserved
I
80
50
Power on
Interruptible point.
81
51
Power off
Interruptible point.
tSee "Processor Detected Faults", later in this chapter.
38
T rap System