Control (Mode 0) - Xerox 550 Reference Manual

16 17 18 19
o
0 :
}
Unassigned.
Special systems control (for customer use
with specially designed equipment).
If bits 16-19 select mode 2 through mode F, CC 1 and CC2
are set to zero and CC3 and CC4 are set according to the
state of the two condition code lines from the external
device.
READ DIRECT, INTERNAL BASIC PROCESSOR
CONTROL (MODE 0)
In this mode, the basic processor is able to read the sense
switches, the basic processor address, and the interrupt in-
hibit bits of the PSWs as follows:
READ SENSE SWITCHES
The following configuration of RD can be used to read the
four SENSE switches in the System Control Processor:
If a parti cular SENSE switch is set, the corresponding bit of
the condition code is set to 1; if a SENSE switch is zero,
the corresponding bit of the condition code is set to 0 (see
IIRead Sense Switches II in Chapter 5).
In this case, only the condition code is affected.
READ BASIC PROCESSOR
The following RD configuration is used to read the basic
processor's address:
If the R field is nonzero, the cluster number in which the
basic processor resides is obtained from the associated pro-
cessor interface and loaded into register R bits 21-23. All
other bits in the register are cleared to zero.
Affected: (R)
Cluster Address - R
21
-
23
0 - R
O - 20 and R 24 - 31
104 Control Instructions
READ INTERRUPT INHIBITS
The following configuration of RD can be used to read the
contents of the interrupt inhibit field:
If the R field of RD is nonzero, the contents of the interrupt
inhibit field (bits 37, 38, 39) of the program status words
are transferred to the least significant 3 bits of the spe-
cified R register (bits 29, 30, 31). The remainder of the R
register (bits 0-28) is cleared to zeros.
Affected: (R)
(PSWs)37_39 - R 29 - 31
0 - R O -
28
Note that a copy of the interrupt inhibits is retained in the
Interrupt Status Register in the Processor Interface associated
with each basic processor.
LOAD FROM LOW MAIN MEMORY
The instruction allows reading the contents of real memory
locations 0-31 (locations 0-15 shadowed by the general
purpose registers). This allows access to the Status Stack
pointer Doubleword in locations 0-1 and the default Pro-
gram Status Words (Interrupt Stack is empty) in locations 2-4.
If the R field is nonzero, the contents of the main memory
locution identifieJ by bits 27-31 Ore loaded
infO
R.
Affected: (R)
EW-R
READ INTERNAL CONTROL REGISTERS
The following configuration of RD is used to read the con-
tents of internal control (or Q) registers:
t i l
i i I I
i
If the R field of the RD instruction is nonzero, the contents
of the internal control register, as specified by the IIQ Ad-
dress
ll
field of the instruction (bit positions 27-31), ore