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5.3 Intel 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
PCI Interface Signals (Continue)
Signal Name
Type
I/OD
PME#
I/O
CLKRUN#
I
REQ[A]#/
GPIO[0]
REQ[B]#/
REQ[5]#/
GPIO[1]
O
GNT[A]#/
GPIO[16]
GNT[B]#/
GNT[5]#/
GPIO[17]
IDE Interface Signals
Signal Name
Type
O
PDCS1#, SDCS1#
O
PDCS3#, SDCS3#
O
PDA[2:0],
SDA[2:0]
Description
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1-M–S5. PME# assertion
can also be enabled to generate an SCI from the S0 state. In some
cases the ICH4 may drive PME# active due to an internal wake
event. The ICH4 will not drive PME# high, but it will be pulled up
to VccSus3_3 by an internal pull-up resistor.
PCI Clock Run: Used to support PCI Clock Run protocol.
Connects to PCI devices that need to request clock re-start, or
prevention of clock stopping.
NOTE: An external pull-up to the core power plane is required.
PC/PCI DMA Request [A:B]: This request serializes ISA-like
DMA Requests for the purpose of running ISA-compatible DMA
cycles over the PCI bus. This is used by devices such as PCI based
Super I/O or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI requests, these signals can be used as
General Purpose Inputs. REQ[B]# can instead be used as the 6th
PCI bus request.
PC/PCI DMA Acknowledges [A: B]: This grant serializes an
ISA-like DACK# for the purpose of running DMA/ISA Master
cycles over the PCI bus. This is used by devices such as PCI based
Super/IO or audio codecs which need to perform legacy 8237 DMA
but have no ISA bus.
When not used for PC/PCI, these signals can be used as General
Purpose Outputs. GNTB# can also be used as the 6th PCI bus
master grant output. These signal have internal pull-up resistors.
Description
Primary and Secondary IDE Device Chip Selects for 100 Range:
For ATA command register block. This output signal is connected
to the corresponding signal on the primary or secondary IDE
connector.
Primary and Secondary IDE Device Chip Select for 300 Range:
For ATA control register block. This output signal is connected to
the corresponding signal on the primary or secondary IDE
connector.
Primary and Secondary IDE Device Address: These output
signals are connected to the corresponding signals on the primary or
secondary IDE connectors. They are used to indicate which byte in
either the ATA command block or control block is being addressed.
IDE Interface Signals (Continue)
Signal Name
Type
I/O
Primary and Secondary IDE Device Data: These signals directly
PDD[15:0],
drive the corresponding signals on the primary or secondary IDE
SDD[15:0]
connector. There is a weak internal pull-down resistor on PDD[7]
and SDD[7].
I
Primary and Secondary IDE Device DMA Request: These input
PDDREQ,
signals are directly driven from the DRQ signals on the primary or
SDDREQ
secondary IDE connector. It is asserted by the IDE device to request
a data transfer, and used in conjunction with the PCI bus master IDE
function and are not associated with any AT compatible DMA
channel. There is a weak internal pull-down resistor on these
signals.
O
Primary and Secondary IDE Device DMA Acknowledge: These
PDDACK#,
signals directly drive the DAK# signals on the primary and
SDDACK#
secondary IDE connectors. Each is asserted by the ICH4 to indicate
to IDE DMA slave devices that a given data transfer cycle (assertion
of DIOR# or DIOW#) is a DMA data transfer cycle. This signal is
used in conjunction with the PCI bus master IDE function and are
not associated with any AT-compatible DMA channel.
O
PDIOR#/
Primary and Secondary Disk I/O Read (PIO and Non-Ultra
(PDWSTB/PRDMA
DMA): This is the command to the IDE device that it may drive
RDY#)
data onto the PDD or SDD lines. Data is latched by the ICH4 on the
deassertion edge of PDIOR# or SDIOR#. The IDE device is
selected either by the ATA register file chip selects (PDCS1# or
SDIOR#/
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
(SDWSTB/SRDMA
IDE DMA acknowledge (PDDAK# or SDDAK#).
RDY#)
Primary and Secondary Disk Write Strobe (Ultra DMA Writes to
Disk): This is the data write strobe for writes to disk. When writing
to disk, ICH4 drives valid data on rising and falling edges of
PDWSTB or SDWSTB. Primary and Secondary Disk DMA Ready
(Ultra DMA Reads from Disk): This is the DMA ready for reads
from disk. When reading from disk, ICH4 deasserts
PRDMARDY# or SRDMARDY# to pause burst data transfers.
O
PDIOW#/
Primary and Secondary Disk I/O Write (PIO and Non-Ultra
(PDSTOP)
DMA): This is the command to the IDE device that it may latch
data from the PDD or SDD lines. Data is latched by the IDE device
on the deassertion edge of PDIOW# or SDIOW#. The IDE device is
SDIOW#/
selected either by the ATA register file chip selects (PDCS1# or
(SDSTOP)
SDCS1#, PDCS3# or SDCS3#) and the PDA or SDA lines, or the
IDE DMA acknowledge (PDDAK# or SDDAK#).
Primary and Secondary Disk Stop (Ultra DMA): ICH4 asserts this
signal to terminate a burst.
97
TECHNICAL SERVICE MANUAL
Description
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