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Prestigio Nobile 150
5.1 Intel Pentium M Processor
CPU Pin Description Continue
Signal Name
Type
I
SMI# (System Management Interrupt) is asserted asynchronously by
SMI#
system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management Mode
(SMM). An SMI Acknowledge transaction is issued, and the processor
begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor will
tristate its outputs.
I
STPCLK# (Stop Clock), when asserted, causes the processor to enter a
STPCLK#
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals to
all processor core units except the system bus and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the processor
restarts its internal clock to all units and resumes execution. The
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an
asynchronous input.
I
TCK (Test Clock) provides the clock input for the processor Test Bus
TCK
(also known as the Test Access Port).
I
TDI (Test Data In) transfers serial test data into the processor. TDI
TDI
provides the serial input needed for JTAG specification support.
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO
TDO
provides the serial output needed for JTAG specification support.
I
TEST1, TEST2, and TEST3 must be left unconnected but should have a
TEST1,
stuffing option connection to V SS separately using 1-k, pull-down
TEST2,
resisitors.
TEST3
Other Thermal Diode Anode.
THERMDA
Other Thermal Diode Cathode.
THERMDC
O
The processor protects itself from catastrophic overheating by use of an
THERMTRIP#
internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature exceeds
approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
I
TMS (Test Mode Select) is a JTAG specification support signal used by
TMS
debug tools.
I
TRDY# (Target Ready) is asserted by the target to indicate that it is
TRDY#
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both system bus agents.
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
TRST#
must be driven low during power on Reset.
Description
CPU Pin Description Continue
Signal Name
Type
I
Processor core power supply.
VCC
I
VCCA provides isolated power for the internal processor core PLL's.
VCCA[3:0]
I
Processor I/O Power Supply.
VCCP
I
Quiet power supply for on die COMP circuitry. These pins should be
VCCQ[1:0]
connected to VCCP on the motherboard. However, these connections
should enable addition of decoupling on the VCCQ lines if necessary.
O
VCCSENSE is an isolated low impedance connection to processor core
VCCSENSE
power (VCC ). It can be used to sense or measure power near the silicon
with little noise.
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of
VID[5:0]
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel Pentium
M processor. The voltage supply for these pins must be valid before the
VR can supply Vcc to the processor. Conversely, the VR output must be
disabled until the voltage supply for the VID pins becomes valid. The
VID pins are needed to support the processor voltage specification
variations.
O
VSSSENSE is an isolated low impedance connection to processor core
VSSSENSE
VSS. It can be used to sense or measure ground near the silicon with
little noise.
85
TECHNICAL SERVICE MANUAL
Description
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