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TECHNICAL SERVICE MANUAL
Core Logic
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SMBus
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Timers
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Turbo 8052 microprocessor based
256 bytes internal RAM
40K bytes embedded programmable flash memory
2K bytes external SRAM
Host interface
Software optional with ISA or LPC interface
Primary programmable I/O address communication port in LPC mode
Support either Parallel IRQ in ISA or SERIRQ in LPC interface
Hardware Fast Gate A20 and KBRST support
Port 92h support
Support 2 SMBus interface for master and slave
Support 4 Timer signal with 3 pre-scalars
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Prestigio Nobile 150
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