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TECHNICAL SERVICE MANUAL
8.2 No Display
P
CORE_CLKEN#
29
+3V
From PU4
R143
L26
L27
L532
L25
FS2
FS1
FS0
CPU
3V66[5:0]
x
0
0
166.66
66.66
x
0
1
100.00
66.66
001
x
1
0
200.00
66.66
x
1
1
133.33
66.66
Mid
0
0
Tristate
Tristate
Mid
0
1
TCLK/2
TCLK/2
Mid
1
0
Reserved
Reserved
Mid
1
1
Reserved
Reserved
0 : 0V
UNIT : MHz
1 : 3.3V
PCICLK_CARD
LPCCLK_KBC
70
J504
P
P
18
U7
Embedded
Controller
MINIPCI
Connector
P
21
U510
17
PCMCIA
Controller
****** System Clock Check ******
+3V
R137
10k
MULTSEL0
R136
0
VTT_PWRGD#
28
8.2K
43
120Z/100M
+3VCLKCPU
46,50
120Z/100M
+3VCLKPCI
8,14
120Z/100M
+3VCLKANA
1,26,37
120Z/100M
+3VCLK66
19,32
+3V
PCI
R148
33.33
4.7K
33.33
FS0
54
33.33
FS1
55
33.33
Tristate
40
FS2
TCLK/2
Reserved
R155
R140
Reserved
4.7K
4.7K
Generator
R617
33
13
R510
PLL207-151
33
16
R620
33
PCICLK_MINIPCI
16
12
C600
10P
3
X501
C603
14.318MHz
10P
2
45
R619
27.4
R616
27.4
44
R626
27.4
49
48
R623
27.4
21
R612
33
R613
33
39
P
4
R622
R625
60.4
60.4
SUSCLK
U508
R744
10K
Clock
29
SMBDATA
30
SMBCLK
39
R611
22
R609
R632
7
R642
56
R621
11
10
R627
116
HSTPCLK#
R595
R615
R618
60.4
60.4
P
5
HCLK_MCH
U504
P
HCLK_MCH#
6
Memory
66M_MCH
Controller
48M_DREFCLK
+1.5V
855GME
R520
1K
Q508
2N7002
+3V
VDD3
R759
R748
R743
2.2K
2.2K
10K
G
S
D
Q522
G
2N7002
S
D
Q521
2N7002
SUSCLK
33
USBCLK_ICH
66M_ICH
33
33
PCICLK_ICH
33
14M_ICH
HSTPCLK#
33
PCICLK_BIOS
33
PCICLK_LAN
Prestigio Nobile 150
P
3
U506
HCLK_CPU
CPU
HCLK_CPU#
Pentium-M
27.4
HTCLK
P
7
J512, J509
DDR SO-DIMM
CLK_DDR[0:5]
CLK_DDR[0:5]#
SMBCLK
SMBDATA
SMB_DATA
P
P
9
10
U12
SMB_CLK
I/O
Controller
Hub
ICH4-M
P
U512
20
31
System BIOS
P
15
U511
115
Ethernet
Controller
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