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TECHNICAL SERVICE MANUAL
5.2 Intel 82855GME Graphics and Memory Controller Hub (GMCH)
DDR SDRAM Interface Descriptions (Continued)
Signal Name
Type
I/O
Data Strobes: Data strobes are used for capturing data. During
SDQS[8:0]
SSTL_2
writes, SDQS is centered on data. During reads, SDQS is edge
aligned with data. The following list matches the data strobe with the
data bytes.
There is an associated data strobe (DQS) for each data signal (DQ)
and check bit
(CB) group.
SDQS[7] -> SDQ[63:56]
SDQS[6] -> SDQ[55:48]
SDQS[5] -> SDQ[47:40]
SDQS[4] -> SDQ[39:32]
SDQS[3] -> SDQ[31:24]
SDQS[2] -> SDQ[23:16]
SDQS[1] -> SDQ[15:8]
SDQS[0] -> SDQ[7:0]
NOTE: ECC error detection is supported by the SDQS[8] signal.
O
Clock Enable: These pins are used to signal a self-refresh or power
SCKE[3:0]
SSTL_2
down command to the DDR SDRAM array when entering system
suspend. SCKE is also used to dynamically power down inactive
DDR SDRAM rows. There is one
SCKE per DDR SDRAM row. These signals can be toggled on every
rising SCK edge.
O
Memory Address Copies: These signals are identical to
SMAB[5,4,2,1]
SSTL_2
SMA[5,4,2,1] and are used to reduce loading for selective
CPC(clock-per-command). These copies are not inverted.
O
Data Mask: When activated during writes, the corresponding data
SDM[8:0]
SSTL_2
groups in the DDR SDRAM are masked. There is one SDM for every
eight data lines. SDM can be sampled on both edges of the data
strobes.
NOTE: ECC error detection is supported by the SDM[8] signal.
O
Clock Output: Reserved, NC.
RCVENOUT#
SSTL_2
O
Clock Input: Reserved, NC.
RCVENIN#
SSTL_2
Description
AGP Addressing Signal Descriptions
Signal Name
Type
I
Pipelined Read: This signal is asserted by the AGP master to
GPIPE#
AGP
indicate a full width address is to be enqueued on by the target using
the AD bus. One address is placed
in the AGP request queue on each rising clock edge while PIPE# is
asserted. When PIPE# is deasserted no new requests are queued
across the AD bus.
During SBA Operation: This signal is not used if SBA (Side Band
Addressing) is selected.
During FRAME# Operation: This signal is not used during AGP
FRAME# operation.
PIPE# is a sustained tri-state signal from masters (graphics
controller), and is an input to the GMCH.
I
Side-band Address: These signals are used by the AGP master
GSBA[7:0]
AGP
(graphics controller) to pass address and command to the GMCH. The
SBA bus and AD bus operate independently. That is, transactions can
proceed on the SBA bus and the
AD bus simultaneously.
During PIPE# Operation: These signals are not used during PIPE#
operation.
During FRAME# Operation: These signals are not used during
AGP FRAME# operation.
NOTE: When sideband addressing is disabled, these signals are
isolated (no external/internal pull-ups are required).
5 contains two mechanisms to queue requests by the AGP master. Note that the master can only use
one mechanism. The master may not switch methods without a full reset of the system. When PIPE# is
used to queue addresses the master isnot allowed to queue addresses using the SBA bus. For example,
during configuration time, if the master indicates that it can use either mechanism, the configuration
software will indicate which mechanism the master will use. Once this choice has been made, the
master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use
the other mode. This change of modes is not a dynamic mechanism, but rather a static decision when
the device is first being configured after reset
88
Prestigio Nobile 150
Description
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