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TECHNICAL SERVICE MANUAL
5. Pin Descriptions of Major Components
5.1 Intel Pentium M Processor
CPU Pin Description
`Signal Name
Type
I/O
A[31:3]# (Address) define a 2 32 -byte physical memory address space.
A[31:3]#
In sub-phase 1 of the address phase, these pins transmit the address of a
transaction. In sub-phase 2, these pins transmit transaction type
information. These signals must connect the appropriate pins of both
agents on the Intel Pentium M processor system bus. A[31:3]# are source
synchronous signals and are latched into the receiving buffers by
ADSTB[1:0]#. Address signals are used as straps which are sampled
before RESET# is deasserted.
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical
A20M#
address bit 20 (A20#) before looking up a line in any internal cache and
before driving a read/write transaction on the bus. Asserting A20M#
emulates the 8086 processor's address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the
ADS#
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents
observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
I/O
Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising
ADSTB[1:0]#
and falling edges. Strobes are associated with signals as shown below.
Signals
REQ[4:0]#, A[16:3]#
A[31:17]#
I
The differential pair BCLK (Bus Clock) determines the system bus
BCLK[1:0]
frequency. All processor system bus agents must receive these signals to
drive their outputs and latch their inputs.
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent
BNR#
that is unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
O
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
BPM[2:0]#
I/O
monitor signals. They are outputs from the processor that indicate the
BPM[3]
status of breakpoints and programmable counters used for monitoring
processor performance. BPM[3:0]# should connect the appropriate pins
of all Intel Pentium M processor system bus agents. This includes debug
or performance monitoring tools.
Description
Associated Strobe
ADSTB[0]#
ADSTB[1]#
CPU Pin Description Continue
Signal Name
Type
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
BPRI#
processor system bus. It must connect the appropriate pins of both
processor system bus agents. Observing BPRI# active (as asserted by
the priority agent) causes the other agent to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by deasserting BPRI#.
I/O
BR0# is used by the processor to request the bus. The arbitration is done
BR0#
between the Intel Pentium M processor (Symmetric Agent) and the
MCH-M (High Priority Agent) of the Intel 855PM or Intel 855GM
chipset.
Analog COMP[3:0] must be terminated on the system board using precision
COMPP3:0]
(1% tolerance) resistors. Refer to the platform design guides for more
implementation details.
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data
D[63:0]#
path between the processor system bus agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four times in
a common clock period. D[63:0]# are latched off the falling edge of
both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals
correspond to a pair of one DSTBP# and one DSTBN#. The following
table shows the grouping of data signals to data strobes and DINV#.
Quad-Pumped Signal Groups
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
Furthermore, the DINV# pins determine the polarity of the data signals.
Each group of 16 data signals corresponds to one DINV# signal. When
the DINV# signal is active, the corresponding data group is inverted and
therefore sampled active high.
O
DBR# (Data Bus Reset) is used only in processor systems where no
DBR#
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system reset. If
a debug port is implemented in the system, DBR# is a no connect.
DBR# is not a processor signal.
82
Prestigio Nobile 150
Description
DSTBN#/DSTBP#
DINV#
0
0
1
1
2
2
3
3
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