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TECHNICAL SERVICE MANUAL
5.1 Intel Pentium M Processor
CPU Pin Description Continue
Signal Name
Type
I
INIT# (Initialization), when asserted, resets integer registers inside the
INIT#
processor without affecting its internal caches or floating-point registers.
The processor then begins execution at the power on Reset vector
configured during power on configuration. The processor continues to
handle snoop requests during INIT# assertion. INIT# is an asynchronous
signal. However, to ensure recognition of this signal following an
Input/Output Write instruction, it must be valid along with the TRDY#
assertion of the corresponding Input/Output Write bus transaction.
INIT# must connect the appropriate pins of both processor system bus
agents. If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST)
I
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of
LINT[1:0]
all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor.
Both signals are asynchronous.
Both of these signals must be software configured using BIOS
programming of the APIC register space and used either as NMI/INTR
or LINT[1:0]. Because the APIC is enabled by default after Reset,
operation of these pins as LINT[1:0] is the default configuration.
I/O
LOCK# indicates to the system that a transaction must occur atomically.
LOCK#
This signal must connect the appropriate pins of both processor system
bus agents. For a locked sequence of transactions, LOCK# is asserted
from the beginning of the first transaction to the end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor system bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of the processor
system bus throughout the bus locked operation and ensure the
atomicity of lock.
O
Probe Ready signal used by debug tools to determine processor debug
PRDY#
readiness.
I
Probe Request signal used by debug tools to request debug operation of
PREQ#
the processor.
O
PROCHOT# (Processor Hot) will go active when the processor
PROCHOT#
temperature monitoring sensor detects that the processor has reached its
maximum safe operating temperature. This indicates that the processor
Thermal Control Circuit has been activated, if enabled.
This signal may require voltage translation on the motherboard.
O
Processor Power Status Indicator signal. This signal is asserted when the
PSI#
processor is in a lower state (Deep Sleep and Deeper Sleep).
Description
CPU Pin Description Continue
Signal Name
Type
I
PWRGOOD (Power Good) is a processor input. The processor requires
PWRGOOD
this signal as a clean indication that the clocks and power supplies are
stable and within their specifications. 'Clean' implies that the signal will
remain low (capable of sinking leakage current), without glitches, from
the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high
state. PWRGOOD can be driven inactive at any time, but clocks and
power must again be stable before a subsequent rising edge of
PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to
protect internal circuits against voltage sequencing issues. It should be
driven high throughout the boundary scan operation.
I
ITP_CLK[1:0] are copies of BCLK that are used only in processor
ITP_CLK[1:0]
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects. These are not processor signals.
I
Asserting the RESET# signal resets the processor to a known state and
RESET#
invalidates its internal caches without writing back any of their contents.
For a power-on Reset, RESET# must stay active for at least two
milliseconds after VCC and BCLK have reached their proper
specifications. On observing active RESET#, both system bus agents
will deassert their outputs within two clocks. All processor straps must
be valid within the specified setup time before RESET# is deasserted.
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
RS[2:0]#
responsible for completion of the current transaction), and must connect
the appropriate pins of both processor system bus agents.
-
These pins are RESERVED and must be left unconnected on the board.
RSVD
However, it is recommended that routing channels to these pins on the
board be kept open for possible future use. Please refer to the platform
design guides for more details.
I
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to
SLP#
enter the Sleep state. During Sleep state, the processor stops providing
internal clock signals to all units, leaving only the Phase-Locked Loop
(PLL) still operating. Processors in this state will not recognize snoops
or interrupts. The processor will recognize only assertion of the
RESET# signal, deassertion of SLP#, and removal of the BCLK input
while in Sleep state. If SLP# is deasserted, the processor exits Sleep
state and returns to Stop-Grant state, restarting its internal clock signals
to the bus and processor core units. If DPSLP# is asserted while in the
Sleep state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
84
Prestigio Nobile 150
Description
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