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TECHNICAL SERVICE MANUAL
5.2 Intel 82855GME Graphics and Memory Controller Hub (GMCH)
Host Interface Signal Descriptions
Signal Name
Type
I/O
Address Strobe: The system bus owner asserts ADS# to indicate the
ADS#
AGTL+
first of two cycles of a request phase. The GMCH can assert this
signal for snoop cycles and
interrupt messages.
I/O
Block Next Request: Used to block the current request bus owner
BNR#
AGTL+
from issuing a new request. This signal is used to dynamically control
the CPU bus pipeline depth.
O
Bus Priority Request: The GMCH is the only Priority Agent on the
BPRI#
AGTL+
system bus. It asserts this signal to obtain the ownership of the
address bus. This signal has priority over symmetric bus requests and
will cause the current symmetric owner to
stop issuing new transactions unless the HLOCK# signal was
asserted.
I/O
Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal
BREQ0#
AGTL+
low during CPURST#. The signal is sampled by the processor on the
active-to-inactive transition of CPURST#. The minimum setup time
for this signal is 4 BCLKs. The minimum hold time is 2 clocks and
the maximum hold time is 20 BCLKs. BREQ0# should be tristated
after the hold time requirement has been satisfied.
During regular operation, the GMCH will use BREQ0# as an early
indication for FSB Address and Ctl input buffer and sense amp
activation.
O
CPU Reset: The CPURST# pin is an output from the GMCH. The
CPURST#
AGTL+
GMCH asserts CPURST# while RESET# (PCIRST# from ICH4-M)
is asserted and for approximately 1 ms after RESET# is deasserted.
The CPURST# allows the processor to begin execution in a known
state.
Note that the ICH4-M must provide CPU strap set-up and hold-times
around CPURST#.
This requires strict synchronization between GMCH, CPURST#
deassertion and ICH4-M driving the straps.
I/O
Data Bus Busy: Used by the data bus owner to hold the data bus for
DBSY#
AGTL+
transfers requiring more than one cycle.
O
Defer: GMCH will generate a deferred response as defined by the
DEFER#
AGTL+
rules of the GMCH's Dynamic Defer policy. The GMCH will also
use the DEFER# signal to indicate a CPU retry response.
Description
Host Interface Signals Continue
Signal Name
Type
I/O
Dynamic Bus Inversion: Driven along with the HD[63:0]# signals.
DINV[3:0]#
AGTL+
Indicates if the associated signals are inverted or not. DINV[3:0]# are
asserted such that the number of data bits driven electrically low (low
voltage) within the corresponding 16-bit group never exceeds 8.
DINV# Data Bits
DINV[3]# HD[63:48]#
DINV[2]# HD[47:32]#
DINV[1]# HD[31:16]#
DINV[0]# HD[16:0]#
I
Deep Sleep #: This signal comes from the ICH4-M device, providing
DPSLP#
CMOS
an indication of C3 and C4 state control to the CPU. Deassertion of
this signal is used as an early indication for C3 and C4 wake up (to
active HPLL). Note that this is a low-voltage
CMOS buffer operating on the FSB VTT power plane.
I/O
Data Ready: Asserted for each cycle that data is transferred.
DRDY#
AGTL+
I/O
Host Address Bus: HA[31:3]# connects to the CPU address bus.
HA[31:3]#
AGTL+
During processor cycles the HA[31:3]# are inputs. The GMCH drives
HA[31:3]# during snoop cycles on behalf of Hub interface.
HA[31:3]# are transferred at 2x rate. Note that the
address is inverted on the CPU bus.
I/O
Host Address Strobe: HA[31:3]# connects to the CPU address bus.
HADSTB[1:0]#
AGTL+
During CPU cycles, the source synchronous strobes are used to
transfer HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.
Strobe Address Bits
HADSTB[0]# HA[16:3]#, HREQ[4:0]#
HADSTB[1]# HA[31:17]#
I/O
Host Data: These signals are connected to the CPU data bus.
HD[63:0]#
AGTL+
HD[63:0]# are transferred at 4x rate. Note that the data signals are
inverted on the CPU bus.
86
Prestigio Nobile 150
Description
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