Table of Contents
Advertisement
Prestigio Nobile 150
5.1 Intel Pentium M Processor
CPU Pin Description Continue
Signal Name
Type
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving
DBSY#
data on the processor system bus to indicate that the data bus is in use.
The data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both processor system bus agents.
I
DEFER# is asserted by an agent to indicate that a transaction cannot be
DEFER#
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or Input/Output agent. This
signal must connect the appropriate pins of both processor system bus
agents.
I/O
DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate
DINV[3:0]#
the polarity of the D[63:0]# signals. The DINV[3:0]# signals are
activated when the data on the data bus is inverted. The bus agent will
invert the data bus signals if more than half the bits, within the covered
group, would change level in the next cycle.
DINV[3:0]# Assignment To Data Bus
Bus Signal
DINV[3]#
DINV[2]#
DINV[1]#
DINV[0]#
I
DPSLP# when asserted on the platform causes the processor to
DPSLP#
transition from the Sleep state to the Deep Sleep state. In order to return
to the Sleep state, DPSLP# must be deasserted. DPSLP# is driven by the
ICH4-M component and also connects to the MCH-M component of the
Intel 855PM or Intel 855GM chipset.
I/O
DRDY# (Data Ready) is asserted by the data driver on each data
DRDY#
transfer, indicating valid data on the data bus. In a multi-common clock
data transfer, DRDY# may be deasserted to insert idle clocks. This
signal must connect the appropriate pins of both processor system bus
agents.
I/O
Data strobe used to latch in D[63:0]#.
DSTBN[3:0]#
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
I/O
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
Signals
D[15:0]#, DINV[0]#
D[31:16]#, DINV[1]#
D[47:32]#, DINV[2]#
D[63:48]#, DINV[3]#
Description
Data Bus Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
Associated Strobe
DSTBN[0]#
DSTBN[1]#
DSTBN[2]#
DSTBN[3]#
Associated Strobe
DSTBP[0]#
DSTBP[1]#
DSTBP[2]#
DSTBP[3]#
CPU Pin Description Continue
Signal Name
Type
I
DPWR# is a control signal from the Intel 855PM and Intel 855GM
DPWR#
chipsets used to reduce power on the Intel Pentium M data bus input
buffers.
O
FERR# (Floating-point Error)/PBE#(Pending Break Event) is a
FERR#/PBE#
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating point when
the processor detects an unmasked floating-point error. FERR# is
similar to the ERROR# signal on the Intel 80387 coprocessor, and is
included for compatibility with systems using MS-DOS* type
floating-point error reporting. When STPCLK# is asserted, an assertion
of FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. When FERR#/PBE# is
asserted, indicating a break event, it will remain asserted until
STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active
will also cause an FERR# break event.
I
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF
GTLREF should be set at 2/3
receivers to determine if a signal is a logical 0 or logical 1.
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
HIT#
I/O
operation results. Either system bus agent may assert both HIT# and
HITM#
HITM# together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
O
IERR# (Internal Error) is asserted by a processor as the result of an
IERR#
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor system bus. This transaction
may optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to
IGNNE#
ignore a numeric error and continue to execute noncontrol floating-point
instructions. If IGNNE# is deasserted, the processor generates an
exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error. IGNNE# has no effect when
the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of
REQ[4:0]#
both processor system bus agents. They are asserted by the current bus
owner to define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
83
TECHNICAL SERVICE MANUAL
Description
. GTLREF is used by the AGTL+
VCCP
Advertisement
Table of Contents
