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5.2 Intel 82855GME Graphics and Memory Controller Hub (GMCH)
Host Interface Signal Descriptions (Continued)
Signal Name
Type
I/O
Differential Host Data Strobes: The differential source synchronous
HDSTBP[3:0]#
AGTL+
strobes are used to transfer HD[63:0]# and DINV[3:0]# at the 4x
HDSTBN[3:0]#
transfer rate.
Strobe Data Bits
HDSTBP[3]#, HDSTBN[3]# HD[63:48]#, DINV[3]#
HDSTBP[2]#, HDSTBN[2]# HD[47:32]#, DINV[2]#
HDSTBP[1]#, HDSTBN[1]# HD[31:16]#, DINV[1]#
HDSTBP[0]#, HDSTBN[0]# HD[15:0]#, DINV[0]#
I/O
Hit: Indicates that a caching agent holds an unmodified version of the
HIT#
AGTL+
requested line. Also, driven in conjunction with HITM# by the target
to extend the snoop window.
I/O
Hit Modified: Indicates that a caching agent holds a modified version
HITM#
AGTL+
of the requested line and that this agent assumes responsibility for
providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
I/O
Host Lock: All CPU bus cycles sampled with the assertion of
HLOCK#
AGTL+
HLOCK# and ADS#, until the negation of HLOCK# must be atomic,
i.e. no Hub interface snoopable access to system memory is allowed
when HLOCK# is asserted by the CPU.
I/O
Host Request Command: Defines the attributes of the request.
HREQ[4:0]#
AGTL+
HREQ[4:0]# are transferred at 2x rate. Asserted by the requesting
agent during both halves of the Request Phase. In the first half the
signals define the transaction type to a level of
detail that is sufficient to begin a snoop request. In the second half the
signals carry additional information to define the complete transaction
type.
The transactions supported by the GMCH Host Bridge are defined in
the Host Interface section of this document.
O
Host Target Ready: Indicates that the target of the processor
HTRDY#
AGTL+
transaction is able to enter the data transfer phase.
O
Response Status: Indicates the type of response according to the
RS[2:0]#
AGTL+
following the table:
RS[2:0]# Response type
000 Idle state
001 Retry response
010 Deferred response
011 Reserved (not driven by GMCH)
100 Hard Failure (not driven by GMCH)
101 No data response
110 Implicit Write back
111 Normal data response
Description
DDR SDRAM Interface Descriptions
Signal Name
Type
O
Chip Select: These pins select the particular DDR SDRAM
SCS[3:0]#
SSTL_2
components during the active state.
NOTE: There is one SCS# per DDR-SDRAM Physical SO-DIMM
device row.
These signals can be toggled on every rising System Memory Clock
edge (SCMDCLK).
O
Multiplexed Memory Address: These signals are used to provide
SMA[12:0]
SSTL_2
the multiplexed row and column address to the DDR SDRAM.
O
Bank Select (Memory Bank Address): These signals define which
SBA[1:0]
SSTL_2
banks are selected within each DDR SDRAM row. The SMA and
SBA signals combine to address every possible location within a
DDR SDRAM device.
O
DDR Row Address Strobe: SRAS# may be heavily loaded and
SRAS#
SSTL_2
requires tw0 DDR SDRAM clock cycles for setup time to the DDR
SDRAMs. Used with SCAS# and SWE# (along with SCS#) to define
the system memory commands.
O
DDR Column Address Strobe: SCAS# may be heavily loaded and
SCAS#
SSTL_2
requires two clock cycles for setup time to the DDR SDRAMs. Used
with SRAS# and SWE# (along with SCS#) to define the system
memory commands.
O
Write Enable: Used with SCAS# and SRAS# (along with SCS#) to
SWE#
SSTL_2
define the DDR SDRAM commands. SWE# is asserted during writes
to DDR SDRAM.
SWE# may be heavily loaded and requires two clock cycles for setup
time to the DDR SDRAMs.
I/O
Data Lines: These signals are used to interface to the DDR SDRAM
SDQ[71:0]
SSTL_2
data bus.
NOTE: ECC error detection is supported: by the SDQ[71:64] signals.
87
TECHNICAL SERVICE MANUAL
Description
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