Table of Contents
Advertisement
S
UPER P3TDLR User's Manual
PS/2 KB/
J28
MOUSE
J27
Parallel
Port
NIC1
NIC2
J14
J15
J11
JP8
J12
JP24
Also see the figure on page 2-7 for the locations of the I/O ports and
2-8 for the Front Control Panel (JF1) connectors.
Figure 1-8A. SUPER P3TDLR Layout
(not drawn to scale)
ATX POWER
FCPGA
Processor
FCPGA
Processor
1
PCI64 #1
PCI64 #2
PCI 1
PCI 2
ATI
RAGE
XL
10.5"
NORTH
BRIDGE
JP2
SW1
1
JP1
AIC-
7892
SOUTH
BRIDGE
BIOS
1-4
JP7
JF1
J23
J26 J24
JP7
JP11
WOM
SUPER
1
I/O
JA1
JBT1
1
WOL JA2
SLED
Advertisement
Table of Contents
