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- Page 1 ® UPER SUPER P6DBS SUPER P6DBE SUPER P6DBU SUPER P6SBU SUPER P6SBS SUPER P6SBA USER’S AND BIOS MANUAL Revision 2.2...
- Page 2 The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes no responsibility for any inaccuracies that may be contained in this document, makes no commitment to update or to keep current the information in this Please Note: For the manual, or to notify any person or organization of the updates.
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Page 3: Manual Organization
Manual Organization Chapter 1, Introduction, describes the features, specifications and perfor- mance of the SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA system board, provides detailed information about the chipset, and offers warranty information. Refer to Chapter 2, Installation, for instructions on how to install the Pentium II processor, the retention mechanism, and the heat sink support. - Page 4 User’s Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Chapter 5 has information on running setup and includes default settings for Standard Setup, Advanced Setup, Chipset function, Power Management, PCI/ PnP Setup and Peripheral Setup. Appendix A offers information on BIOS error beep codes and messages.
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Page 5: Table Of Contents
SUPER P6DBU ..................1-5 SUPER P6SBU ..................1-6 SUPER P6SBS ..................1-7 SUPER P6SBA ..................1-8 SUPER P6DBS Motherboard Layout ............1-9 SUPER P6DBE Motherboard Layout ............. 1-10 SUPER P6DBU Motherboard Layout ............. 1-11 SUPER P6SBU Motherboard Layout ............. 1-12 SUPER P6SBS Motherboard Layout ............. - Page 6 User’s Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Precautions ....................2-1 Unpacking ....................2-1 Pentium II Processor Installation ..............2-1 OEM Pentium II and Heat Sink Support ..........2-4 Removing the Pentium II Processor ............2-4 Installation of the Universal Retention Mechanism ........2-5 Special Instructions for the Celeron Processor .........
- Page 7 Table of Contents Troubleshooting Procedures ................3-1 Before Power On ..................3-1 Troubleshooting Flowchart ..............3-1 No Power ....................3-2 No Video ..................... 3-2 Memory Error ..................... 3-2 Losing the System’s Setup Configuration ..........3-3 Technical Support Procedures ..............3-3 Frequently Asked Questions ................
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Page 8: Jumper Quick Reference
User’s Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Jumper Quick Reference P6DBS/P6DBE/P6SBS/P6SBA P6DBU/P6SBU Jumpers Function Page Function Page Jumpers JB1, JB2, JB3, JB4 CPU/Bus Ratio Selection JB1, JB2, JB3, JB4 CPU/Bus Ratio Selection 1-11 JBT1 CMOS Clear JBT1 CMOS Clear JP20 Power On/Off State... -
Page 9: Front Control Panel Connector
User’s Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Front Control Panel Connector JF2 JF1 Hard Hard Drive Drive IR Con Power Power Keyboard Keyboard lock lock Power On Speaker Speaker Reset IR Com Please see pages 2-6 and 2-7 for pin definitions. Power On... -
Page 11: Chapter 1: Introduction
SDRAM, concurrent PCI and Ultra DMA 33 MB/s burst data transfer rate. While all of the motherboards are ATX form factor, P6DBU and P6DBE have 5 PCI and 2 ISA with one shared slot. SUPER P6DBS, P6SBU, P6SBS and P6SBA have 4 PCI and 3 ISA with one shared slot. - Page 12 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA on-board Adaptec 7895 MultiChannel UW SCSI controller. The dual chan- nels allow data transfer rate of 40 MB/s per channel. Additionally, these two motherboards have a RAID port on-board to support the Adaptec ARO- 1130SA/CA RAIDport II card for increase I/O performance and fault toler-...
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Page 13: Super P6Dbs
Chapter 1: Introduction SUPER P6DBS Figure 1-1. SUPER P6DBS Motherboard Picture... -
Page 14: Super P6Dbe
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA SUPER P6DBE Figure 1-2. SUPER P6DBE Motherboard Picture... -
Page 15: Super P6Dbu
Chapter 1: Introduction SUPER P6DBU Figure 1-3. SUPER P6DBU Motherboard Picture... -
Page 16: Super P6Sbu
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA SUPER P6SBU Figure 1-4. SUPER P6SBU Motherboard Picture... -
Page 17: Super P6Sbs
Chapter 1: Introduction SUPER P6SBS Figure 1-5. SUPER P6SBS Motherboard Picture... -
Page 18: Super P6Sba
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA SUPER P6SBA Figure 1-6. SUPER P6SBA Motherboard Picture... -
Page 19: Super P6Dbs Motherboard Layout
1-2 Auto x5.5 2-3 66 MHz OFF 100 MHz ——–—–———————————————— JP20: 1-2 PIIX CTL PD State 2-3 BIOS CTL PD State (default) WOL: Wake-on-LAN ——–———————–——–—–——–——–— *Note: To Enable Overheat Buzzer place a jumper on BZ_On. Figure 1-7. SUPER P6DBS Motherboard Layout... -
Page 20: Super P6Dbe Motherboard Layout
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA 9.6" PS/2 KB PS/2 MOUSE PWR_SEC J17, J18 Overheat LED JOH1 BZ_ON Parallel Port FLOPPY JP16 IDE 1 12" 12" JP11 JP20 PCI 5 JBT2: Ext Battery PCI 4 Chassis Intrusion PCI 3 PIIX4E PCI 2 JP18... -
Page 21: Super P6Dbu Motherboard Layout
Chapter 1: Introduction 9.65" PWR_SEC PS/2 KB PS/2 MOUSE J17, J18 BZ_ON Overheat LED Parallel Port FLOPPY JP11 JP20 JBT2: Ext Battery JA5, JA6: SCSI Termination S-TERM PCI 4 IDE 1 PCI 3 Chassis Intrusion PIIX4E PCI 2 SLED JBT1 PCI 1 RAID PORT SBLINK... -
Page 22: Super P6Sbu Motherboard Layout
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA 8.875" PS/2 KB PS/2 MOUSE JOH: Overheat LED J17, J18 JA5, JA6: SCSI Termination Parallel Port S-TERM FLOPPY IDE 1 JP11 12" 3860 12" 1938 UA10 PCI 4 JBT2: Ext Battery JPSI 7890 PCI 3 PIIX4E PCI 2... -
Page 23: Super P6Sbs Motherboard Layout
Chapter 1: Introduction 8.875" PS/2 KB PS/2 MOUSE JOH: Overheat LED J17, J18 JA5, JA6: SCSI Termination Parallel Port 12" Chassis 12" Intrusion FLOPPY IDE 1 JP11 PCI 4 JBT2: Ext Battery PCI 3 PIIX4E SCSI LED PCI 2 SBLINK PCI 1 RAID PORT JP20... -
Page 24: Super P6Sba Motherboard Layout
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA 7" PS/2 KB PS/2 MOUSE CPU FAN J17, J18 FLOPPY Parallel Port RESET JP11 SPEA- LOCK 12" IDE 1 12" JP20 JL1: Chassis Intrusion JOH: Overheat LED JBT2: Ext Battery PCI 4 PCI 3 JBT1 PCI 2... -
Page 25: Bx Agp Set: System Block Diagram
Chapter 1: Introduction Host Bus SDRAM 440BX Port PCI Slots SMBus APIC PIIX4E IDE Ports Power SCSI Management Ports ISA Slots BIOS Figure 1-13. 440BX AGP SET: System Block Diagram (Dual Processors) 1-15... - Page 26 Features and P6SBA Motherboards* * Bolded text notes variation in features. The following list covers the general features of SUPER P6DBS, P6DBE, P6DBU, P6SBU, P6SBS, and P6SBA. • Dual Pentium II processor 233/266/300/333 MHz at 66 MHz bus speed or 350/400 MHz at 100 MHz bus speed (Note: SUPER P6SBU, P6SBS, and P6SBA support a Single Pentium II processor.)
- Page 27 • SUPER Doctor Utility • SCSI Utility, manual and driver Dimensions • SUPER P6DBS - ATX (12" x 9.65") * See board diagram for full measurements • SUPER P6DBE - ATX (12" x 9.6") • SUPER P6DBU - ATX (12" x 9.65") * See board diagram for full measurements •...
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Page 28: Chipset Overview
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Chipset Overview The 440BX chipset, developed by Intel, is the ultimate processor platform targeted for 3D graphics and multimedia applications. Along with System- to-PCI bridge integrated with optimized DRAM controller and data path, the chipset introduces the Accelerated Graphics Port (AGP) interface. - Page 29 Chapter 1: Introduction Environment Temperature Control The thermal control sensor will monitor the real-time CPU temperature. It will turn on the back-up fan whenever the CPU temperature goes over the user- defined threshold. The overheat circuitry runs independently from the CPU. It can still monitor the overheat condition even if the CPU is in sleep mode.
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Page 30: Solo-1 Pci Audiodrive
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Hardware BIOS Virus Protection The system BIOS is protected by hardware so that no virus can infect the BIOS area. The user can only change the BIOS content through the flash utility provided by SUPERMICRO. This feature can prevent viruses from infecting the BIOS area and loss of valuable data. -
Page 31: Acpi/Pc 98 Features
Chapter 1: Introduction synthesizer, DMA control logic with FIFO, and PCI bus interface logic. There are three stereo inputs (LINE-IN, LINE-OUT, MIC IN) and a mono microphone input. ACPI/PC 98 Features ACPI stands for Advanced Configuration and Power Interface. The ACPI specification defines a flexible and abstract hardware interface that pro- vides a standard way to integrate power management features throughout a PC system, including hardware, operating system and application soft-... -
Page 32: W Ake-On-Lan
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Real Time Clock Wake-up Alarm The PC is perceived to be off when not in use, but is still capable of responding to preset wake-up events. In the BIOS the user can set a timer to wake-up the system at a predetermined time. -
Page 33: Super I/O
Chapter 1: Introduction SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA accommodates ATX power supplies. Although most power supplies generally meet the specifi- cations required by the CPU, some power supplies are not adequate. It is highly recommended that you use a high quality power supply which meets ATX power supply specification 2.01. - Page 34 ACPI and DPM (Device Power Management). AIC -7895 MultiChannel single-chip UltraSCSI SUPER P6DBS/P6SBS has an on-board SCSI controller which is 100% com- patible with all major operating and hardware platforms. PCI 2.1 and SCAM Level 1 compliance are assured.
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Page 35: Warranty, Technical Support, And Service
Chapter 1: Introduction The AIC-7890 Ultra2 SCSI controller, used together with the AIC-3860 trans- ceiver, allows Ultra2 and single-ended devices to operate together on the same SCSI bus without inpacting Ultra2 performance and cable lengths. The AIC-7890 controller can support external High Voltage Differential (HVD) transceivers only for Ultra data rates. -
Page 36: Returns
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Returns If you must return products for any reason, refer to Chapter 3 in this manual, “Returning Merchandise for Service.” 1-26... -
Page 37: Chapter 2: Installation
Chapter 2: Installation Chapter 2 Installation Static-Sensitive Devices Static-sensitive electric discharge can damage electronic components. prevent damage to your system board, it is important to handle it very carefully. The following measures are generally sufficient to protect your equipment from static discharge. Precautions •... - Page 38 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA 2. Install the retention mechanism attach mount under the motherboard. Do this before mounting the motherboard into the chassis. Do not screw too tightly. Mount the two black plastic pegs onto the motherboard (Figure 2.1). These pegs will be used to attach the fan heatsink supports.
- Page 39 Chapter 2: Installation alignment notch in the SEC cartridge fits over the plug in Slot 1. Push the processor down firmly, with even pressure on both sides of the top, until it is seated. Figure 2-2. Retention Mechanism Top of Processor Do not screw too tightly! 6.
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Page 40: Oem Pentium Ii And Heat Sink Support
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Figure 2-3. Attaching the Fan Power Cable OEM Pentium II and Heat Sink Support The heat sink support consists of a top bar, a base bar, four posts on the top bar and two posts on the base bar. -
Page 41: Installation Of The Universal Retention Mechanism
Chapter 2: Installation When removing the Pentium II processor, avoid pressing down on the motherboard or components. Instead, press down on the plastic connectors. Installation of the Universal Retention Mechanism (URM) Please Note! Screws and washers attach from the bottom of the board and must be installed before mounting the board to the chassis. - Page 42 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Figure 2-5 URM and Celeron Installation Supero Screw holes for retention URM with arms folded mechanism Note: Left and Right arms are defined Note notch in socket Top view of Celeron cap...
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Page 43: Explanation And Diagram Of Jumper/Connector
Chapter 2: Installation Explanation and Diagram of Jumper/ Connector Connector Pins To modify the operation of the motherboard, jumpers can be used Jumper to choose settings. Jumpers cre- ate shorts between two pins and change the function of the con- Setting nector. -
Page 44: Mounting The Motherboard In The Chassis
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Mounting the Motherboard in the Chassis All the motherboards have standard mounting holes to fit different types of chassis. Chassis may come with a variety of mounting fasteners, made of metal or plastic. Although a chassis may have both metal and plastic fas- teners, metal fasteners are the most highly recommended because they ground the system board to the chassis. -
Page 45: Pw_On Connector
Chapter 2: Installation PW_ON Connector The PW_ON connector is located on pins 9 and 10 of JF2. Momen- Table 2-5 tarily contacting both pins will PW-ON Connector Pin Definitions power on/off the system. for JF2 user can also configure this but- ton to function as a suspend but- Number Definition... -
Page 46: Speaker Connector
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Table 2-9 Speaker Connector Speaker Connector Pin Definitions for The speaker connector is located Number Function Definition on pins 10 to 13 of JF1. See Table Red wire, Speaker data No connection 2-9 for pin definitions. Speaker data Power Save State Select Refer to Table 2-10 to set JP20. -
Page 47: Atx Serial Ports
Chapter 2: Installation ATX Serial Ports Table 2-13 ATX Serial Ports Pin Definitions ATX serial port COM1 is located Pin Number Definition Pin Number Definition on J20 and serial port COM2 is located on J21. See Table 2-13 Serial In Ground for pin definitions. -
Page 48: Chassis Intrusion
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Chassis Intrusion Table 2-18 Chassis Intrusion The Chassis Intrusion Detector is Detector Settings on located on JL1. See chapter one, board layouts, and PC Health Moni- Number Definition Intrusion Input tor page 1-18 for more information. Ground See Table 2-18 for pin definitions. - Page 49 Chapter 2: Installation Side View of DIMM Installation into Socket PC100 PC100 To Install: Notches Notches Insert DIMM vertically, press down until it snaps into place. Note: Notches should align Pay attention with the to the two receptive points on the socket notches.
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Page 50: Parallel Port Connector
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA two hard disk drives and the SCSI adapter. (Note: most SCSI hard drives are single-ended SCSI devices.) The SCSI ID is determined by jumpers or a switch on the SCSI device. The last internal (and external) SCSI device cabled to the SCSI adapter must be terminated. -
Page 51: Scsi Connectors
Chapter 2: Installation Table 2-22 68-pin Single End SCSI Connector Pin Pin Number Function Pin Number Function -DB (12) -DB (13) -DB (14) -DB (15) Parity H SCSI Connectors -DB (0) -DB (1) -DB (2) There are no jumpers to configure -DB (3) -DB (4) the on-board Single End SCSI in-... -
Page 52: Scsi Lvd 68-Pin Connector
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Table 2-24 SCSI LVD 68-pin Connector Connector Connector Contact Contact Number Signal Names Number Signal Names +DB(12) -DB(12) +DB(13) -DB(13) +DB(14) -DB(14) +DB(15) -DB(15) +DB(P1) -DB(P1) +DB(0) -DB(0) +DB(1) -DB(1) +DB(2) -DB(2) +DB(3) -DB(3) +DB(4) -DB(4) +DB(5) -
Page 53: Agp Port
Chapter 2: Installation Table 2-25 AGP Port Pin Definitions for J8 Pin # Pin # Spare Vddq3.3 Vddq3.3 5.0V Spare AD21 AD22 5.0V Reserved* AD19 AD20 USB+ USB- AD17 AD18 INTB# INTA# C/BE2# AD16 RST# Vddq3.3 Vddq3.3 REQ# GNT# IRDY# Frame# VCC3.3 VCC3.3... - Page 54 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA 2-18...
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Page 55: Chapter 3: Troubleshooting
Chapter 3: Troubleshooting Chapter 3 Troubleshooting Troubleshooting Procedures Use the following procedures and chart to troubleshoot your system. If you have followed all of the procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/or ‘Returning Merchandise for Service’... -
Page 56: No Power
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA No Power Make sure the default jumper is on and CPU is correctly setup. Turn power switch on and off to test system. If power is still not on, turn off system power to move jumper setting on JP20 from 2-3 to 1-2. -
Page 57: Losing The System's Setup Configuration
Chapter 3: Troubleshooting Losing the System’s Setup Configuration Check the jumper JBT1 setting. Ensure that you are using a high quality power supply. A poor quality power supply may cause the system to lose CMOS setup. Refer to Chapter 1 of this manual for details. -
Page 58: Frequently Asked Questions
Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Frequently Asked Questions Question: What are the differences between the various memo- ries that the 440BX motherboard can support? Answer: The 440BX integrates a main memory DRAM controller that sup- ports a 64-bit or 72-bit (64 bit memory data plus 8 ECC bits.) DRAM from 8 MB to 512 MB for SDRAM and from 8 MB to 1 GB for EDO or registered DIMM. - Page 59 What is the correct memory to use and which BIOS setting should I choose? Answer: The correct memory to use on the SUPER P6DBS/P6DBE/P6DBU/ P6SBU/P6SBS/P6SBA is 168-pin DIMM 3.3v non-buffered SPD (Serial Present Detection) SDRAM, SDRAM and EDO memory. SPD SDRAM is preferred but is not necessary.
- Page 60 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA Question: Do I need the CD that came with your motherboard? Answer: The supplied compact disc has quite a few drivers and programs that will greatly enhance your system. We recommend that you review the CD and install the applications you need.
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Page 61: Returning Merchandise For Service
Chapter 3: Troubleshooting Returning Merchandise for Service A receipt or copy of your invoice marked with the date of purchase is required before any warranty service will be rendered. You can obtain service by calling your vendor for a Returned Merchandise Authorization (RMA) number. - Page 62 Manual SUPER P6DBS/P6DBE/P6DBU/P6SBU/P6SBS/P6SBA...
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Page 63: Chapter 4: Ami Bios
Chapter 4: AMI BIOS Chapter 4 AMI BIOS Introduction This chapter describes the AMIBIOS for the Intel 440BX Pentium II 400/350/ 333/300/266/233 MHz processors. The AMI ROM BIOS is stored in the Flash EEPROM and is easily upgraded using a floppy disk-based program. System BIOS ®... -
Page 64: Bios Features
BIOS User's Manual American AMIBIOS (c) 1997 American Megatrends, Inc. Mega Trends 0404981500 Pentium II Motherboard Made in USA R1.0 UPER BIOS date code Checking NVRAM xxxxx KB OK BIOS revision code Hit <DEL> if you want to run SETUP (C) Super Micro Computer, Inc., XX-XXXX-XXXXXX-XXXXXXXX-XXXXXX-XXXX-X BIOS Features... -
Page 65: Bios Configuration Summary Screen
Chapter 4: AMI BIOS • five positive voltage inputs • two negative voltage inputs • three fan speed monitoring inputs BIOS Configuration Summary Screen AMIBIOS displays a screen that looks similar to the following when the POST routines complete successfully. AMIBIOS System Configuration (C) 1985-1997 American Megatrends Inc., Main Processor : Pentium(tm) II... - Page 66 BIOS User's Manual Figure 4-1. Standard Option Highlighted Figure 4-2. Settings for Standard Option...
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Page 67: Chapter 5: Running Setup
Chapter 5: Running Setup Chapter 5 Running Setup* *Optimal and Fail-Safe default settings are bolded in text unless otherwise noted. The WinBIOS Setup options described in this section are selected by choosing the appropriate high-level icon from the Standard Setup screen. All displayed icons are described in this section, although the screen display is often all you need to understand how to set the options. - Page 68 BIOS User's Manual is best to select Auto to allow AMIBIOS to determine the PIO mode. If you select a PIO mode that is not supported by the IDE drive, the drive will not work properly. If you are absolutely certain that you know the drive's PIO mode, select PIO mode 0-4, as appropriate Select Type.
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Page 69: Advanced Setup
Chapter 5: Running Setup Date and Time Configuration Select the Standard option. Select the Date/Time icon. The current values for each category are displayed. Enter new values through the keyboard. Floppy A Floppy B Choose the Floppy Drive A or B icon to specify the floppy drive type. The settings are Not Installed, 360 KB 5¼... - Page 70 BIOS User's Manual Pri Master ARMD Emulated as Pri Slave ARMD Emulated as Sec Master ARMD Emulated as Sec Slave ARMD Emulated as Options for Pri Master ARMD Emulated as, Pri Slave ARMD Emulated as, Sec Master ARMD Emulated as and Sec Slave ARMD Emulated as are Auto, Floppy or Hard disk.
- Page 71 Chapter 5: Running Setup been tried for booting). If selected as No and all selected boot devices failed to boot, the BIOS will try not to boot from the other boot devices which may be present but not selected as boot devices in setup. Initial Display Mode This option determines the display screen with which the POST is going to start the display.
- Page 72 BIOS User's Manual PS/2 Mouse Support Settings for this option are Enabled or Disabled. When this option is set to Enabled, AMIBIOS supports a PS/2-type mouse. Primary Display This option specifies the type of display adapter card installed in the system.
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Page 73: Chipset Setup
Chapter 5: Running Setup C000, 16K Shadow C400, 16K Shadow These options specify how the 32 KB of video ROM at C0000h is treated. The settings are: Disabled, Enabled or Cached. When set to Disabled, the contents of the video ROM are not copied to RAM. When set to Enabled, the contents of the video ROM area from C0000h-C7FFFh are copied (shadowed) from ROM to RAM for faster execution. - Page 74 BIOS User's Manual tions: - In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during initialization should be ignored. - The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI cycle - The 82443BX can also assert SERR# when a PCI parity error occurs during the address or data phase...
- Page 75 Chapter 5: Running Setup Multi-Trans Timer (Clks) This option specifies the multi-trans latency timings (in PCI clocks) for devices in the computer. It reduces overhead switching between different masters. The settings are Disabled, 32, 64, 96, 128, 160, 192 or 224. PCI1 to PCI0 Access PCI1 refers to AGP in BX and LX chipsets.
- Page 76 BIOS User's Manual AMIBIOS automatically enables the System Management Interface (SMI). If you do not want to enable power management, set the Power Management/APM option to Disabled and set all Power Management Setup timeout options to Disabled. To enable power management, set Power Management/APM to Enabled and set the power management timeout options as desired.
- Page 77 Chapter 5: Running Setup ACPI Control Register The settings for this option are Enabled or Disabled. Set this option to Enabled to enable the ACPI (Advanced Configuration and Power Inter- face) control register. Gated Clock Signal GCLKEN enables internal dynamic clock gating in the 82443BX when a AGPset "IDLE"...
- Page 78 BIOS User's Manual 8bit I/O Recovery Time This option specifies the length of a delay inserted between consecutive 8-bit I/O operations. The settings are Disabled, 1 SYSCLK, 2 SYSCLKs, 3 SYSCLKs, 4 SYSCLKs, 5 SYSCLKs, 6 SYSCLKs, 7 SYSCLKs or 8 SYSCLKs.
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Page 79: Power Management
Chapter 5: Running Setup DMA5 Type DMA6 Type DMA7 Type These options specify the bus that the specified DMA channel can be used on. The settings are PC/PCI, Distributed, or Normal ISA. Memory Buffer Strength The settings for this option are Strong or Auto. Manufacturer's Setting Note: The user should always set this option to mode 0. - Page 80 BIOS User's Manual Hard Disk Power Down Mode This option specifies the power conserving state that the hard disk drive enters after the specified period of hard drive inactivity has expired. settings are Disabled, Standby, or Suspend. Note: The Optimal default setting for this option is Suspend and the Fail-Safe default setting is Disabled.
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Page 81: Pci/Pnp Setup
Chapter 5: Running Setup no display activity for the length of time specified in the Standby Timeout (Minute) option, the computer enters a power savings state. The settings are Monitor or Ignore. Device 6 (Serial port 1) Device 7 (Serial port 2) Device 8 (Parallel port) Device 5 (Floppy disk) Device 0 (Primary Master IDE) - Page 82 BIOS User's Manual PCI VGA Palette Snoop The settings for this option are Disabled or Enabled. W hen set to Enabled, multiple VGA devices operating on different buses can handle data from the CPU on each set of palette registers on every video device. Bit 5 of the command register in the PCI device configuration space is the VGA Palette Snoop bit (0 is disabled).
- Page 83 Chapter 5: Running Setup PCI Slot1 IRQ Priority PCI Slot2 IRQ Priority PCI Slot3 IRQ Priority PCI Slot4 IRQ Priority These options specify the IRQ priority for PCI devices installed in the PCI expansion slots. The settings are Auto, (IRQ) 3, 4, 5, 7, 9, 10, or 11, in priority order.
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Page 84: Peripheral Setup
BIOS User's Manual Reserved Memory Size This option specifies the size of the memory area reserved for legacy ISA adapter cards. The settings are Disabled, 16K, 32K or 64K. Reserved Memory Address This option specifies the beginning address (in hex) of the reserved memory area. - Page 85 Chapter 5: Running Setup H/W Monitor In4 (+12V) H/W Monitor In5 (-12V) H/W Monitor In6 (-5V) CPU1 Fan CPU2 Fan Thermal Control Fan The above features are for PC Health Monitoring. The motherboards with W83781D have seven on-board voltage monitors for the CPU core, CPU I/ O, +3.3V, +5V, -5V, +12V, and -12V, and three fan status monitors.
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Page 86: Security Setup
BIOS User's Manual the host device. Use ECP (Extended Capabilities Port) to achieve data transfer rates of up to 2.5 Mbps. ECP uses the DMA protocol and provides symmetric bidirectional communication. Note: The Optimal default setting for this option is ECP and the Fail-Safe setting is N o r m a l . -
Page 87: Utility Setup
Chapter 5: Running Setup When you select Supervisor or User, AMIBIOS prompts for a password. You must set the Supervisor password before you can set the User password. Enter a 1-6 character password. The password does not appear on the screen when typed. Retype the new password as prompted and press <Enter>. - Page 88 BIOS User's Manual 5-22...
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Page 89: Appendix A: Bios Error Beep Codes
Appendix A: BIOS Error Beep Codes Appendix A BIOS Error Beep Codes & Messages During the POST (Power-On Self-Test) routines, which are performed each time the system is powered on, errors may occur. Non-fatal errors are those which, in most cases, allow the system to continue the boot-up process. - Page 90 BIOS User’s Manual Beeps Error message Description Refresh Failure The memory refresh circuitry on the motherboard is faulty. Parity Error A parity error was detected in the base memory (the first 64 KB block) of the system. Base 64 KB Memory Failure A memory failure occurred within the first 64 KB of memory.
- Page 91 Appendix A: BIOS Error Beep Codes If it beeps... then ... 1, 2, 3 times reseat the DIMM memory. If the system still beeps, replace the memory. 6 times reseat the keyboard controller chip. If it still beeps, replace the keyboard controller.
- Page 92 BIOS User’s Manual Error Message Information 8042 Gate -- A20 Gate A20 on the keyboard controller (8042) Error is not working. Replace the 8042. Address Line Short! Error in the address decoding circuitry on the motherboard. C: Drive Error Hard disk drive C: does not respond. Run the Hard Disk Utility to correct this problem.
- Page 93 Appendix A: BIOS Error Beep Codes Error Message Information CMOS Time and Run Standard Setup to set the date and time Date Not Set in CMOS RAM. D: Drive Error Hard disk drive D: does not respond. Run the Hard Disk Utility. Also check the D: hard disk type in Standard Setup to make sure that the hard disk drive type is correct.
- Page 94 BIOS User’s Manual Error Message Information Invalid Boot Diskette The BIOS can read the disk in floppy drive A:, but cannot boot the computer. Use another boot disk. Keyboard Is Locked... The keyboard lock on the computer is Unlock It engaged.
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Page 95: Appendix B: Ami Bios Post Diagnostic Error
Appendix B: AMI BIOS POST Diagnostics Error Messages Appendix B AMI BIOS POST Diagnostic Error Messages This section describes the power-on self-tests (POST) port 80 codes for the AMI BIOS. Check Point Description Code copying to specific areas is done. Passing control to INT 19h boot loader next. - Page 96 BIOS User’s Manual Check Point Description keyboard controller command byte written. Next, issuing the pin 23 and 24 blocking and unblocking commands. Next, checking if the <End or <Ins> keys were pressed during power Initializing CMOS Initialize CMOS every boot AMIBIOS POST option...
- Page 97 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description Initialization before setting the video mode is complete. Configuring monochrome mode color mode settings next. Bus initialization system, static, output devices will be done next, if present. Passing control video perform required configuration before the video ROM test.
- Page 98 BIOS User’s Manual Check Point Description Initializing the bus input, IPL, and general devices next, if present. Displaying bus initialization error messages. cursor position been read saved. Displaying the Hit <DEL> message next. Preparing the descriptor tables next. The descriptor tables are prepared. Entering protected mode for the memory test next.
- Page 99 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description The memory below 1 MB has been cleared via a soft reset. Clearing the memory above 1 MB next. The memory above 1 MB has been cleared via a soft reset.
- Page 100 BIOS User’s Manual Check Point Description The DMA page register test passed. Performing the DMA Controller 1 base register test next. controller base register test passed. Performing the DMA controller 2 base register test next. controller base register test passed. Programming DMA controllers 1 and 2 next.
- Page 101 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description programming before WINBIOS Setup been completed. Uncompressing WINBIOS Setup code executing AMIBIOS Setup W INBIOS Setup utility next. Returned from WINBIOS Setup and cleared the screen. Performing necessary programming after WINBIOS Setup next.
- Page 102 BIOS User’s Manual Check Point Description Any initialization required after the option ROM test has been completed. Configuring the timer data area and printer base address next. Set the timer and printer base addresses. Setting the RS-232 base address next. Returned after setting...
- Page 103 Appendix B: AMI BIOS POST Diagnostics Error Messages Check Point Description Returned from adaptor E000h control. Next, performing initialization required after the E000 option ROM had control. Initialization after E000 option control completed. Displaying the system configuration next. Building multiprocessor table, necessary.
- Page 104 BIOS User’s Manual If either <Ctrl><Home>was pressed or the system BIOS checksum is bad, next the system will go to checkpoint code E0h. Otherwise, going to checkpoint code D7h. B-10...
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